Patents by Inventor Lu PING
Lu PING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923041Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.Type: GrantFiled: July 5, 2022Date of Patent: March 5, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
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Publication number: 20240072352Abstract: An enclosure for a rechargeable energy storage system (RESS) includes a hermetic sealing enclosure and a structural housing component configured to support the hermetic sealing enclosure. The hermetic sealing enclosure is arranged on the structural housing component. The hermetic sealing enclosure is configured to house the RESS and provide a hermetic seal.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Hui-ping WANG, Lu HUANG, William P. PAYNE, Hui WANG, Blair E. CARLSON
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Publication number: 20240021225Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
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Publication number: 20230352085Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.Type: ApplicationFiled: June 29, 2023Publication date: November 2, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
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Patent number: 11793823Abstract: A compound of Formula (I): or a pharmaceutically acceptable salt thereof, in which Ring X is a 3 to 7 membered monocyclic ring, at least one of R1, R2, R3, and R4 is OR5 or CH2OR5 and the other R1, R2, R3, and R4 each independently are halogen, OH, OR5, CH2OR5, CO2H, OC?OR6, (C?O)R6, R6, C1-10 alkyl, C2-10 alkenyl, C2-10 alkynyl, H, or absent. Also provided herein are therapeutic uses of the compound of Formula (I).Type: GrantFiled: March 21, 2022Date of Patent: October 24, 2023Assignee: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
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Patent number: 11779561Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.Type: GrantFiled: February 1, 2022Date of Patent: October 10, 2023Assignee: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
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Patent number: 11735251Abstract: A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.Type: GrantFiled: February 23, 2021Date of Patent: August 22, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li Yang, Lu-Ping Kong, Kuan Cheng, He-Zhou Wan
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Publication number: 20230122135Abstract: A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: Xiu-Li YANG, He-Zhou WAN, Lu-Ping KONG, Wei-Yang JIANG
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Patent number: 11557336Abstract: A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.Type: GrantFiled: November 30, 2020Date of Patent: January 17, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li Yang, He-Zhou Wan, Lu-Ping Kong, Wei-Yang Jiang
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Patent number: 11492546Abstract: Herein are described two-dimensional metal organic frameworks (2D MOFs). The 2D MOFs includes a plurality of multivalent metals or metal ions and a plurality of multidentate ligands arranged to form a crystalline structure having a lateral size of at least about 2.5 ?m and a thickness of less than about 5 nm. Herein are also described methods for preparing the 2D MOFs. The 2D MOFs can be used, for example, in electrochromic devices such as smart windows and flexible displays.Type: GrantFiled: October 23, 2020Date of Patent: November 8, 2022Assignee: TRUSTEES OF BOSTON UNIVERSITYInventors: Xi Ling, Ran Li, Lu Ping
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Publication number: 20220335992Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
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Patent number: 11398261Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.Type: GrantFiled: January 25, 2021Date of Patent: July 26, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
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Publication number: 20220218730Abstract: A compound of Formula (I): or a pharmaceutically acceptable salt thereof, in which Ring X is a 3 to 7 membered monocyclic ring, at least one of R1, R2, R3, and R4 is OR5 or CH2OR5 and the other R1, R2, R3, and R4 each independently are halogen, OH, OR5, CH2OR5, CO2H, OC?OR6, (C?O)R6, R6, C1-10 alkyl, C2-10 alkenyl, C2-10 alkynyl, H, or absent. Also provided herein are therapeutic uses of the compound of Formula (I).Type: ApplicationFiled: March 21, 2022Publication date: July 14, 2022Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
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Patent number: 11382924Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.Type: GrantFiled: July 16, 2021Date of Patent: July 12, 2022Assignee: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
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Publication number: 20220189541Abstract: A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.Type: ApplicationFiled: February 23, 2021Publication date: June 16, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
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Publication number: 20220165315Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.Type: ApplicationFiled: January 25, 2021Publication date: May 26, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
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Publication number: 20220157993Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Inventors: Cheng-Ta YANG, Lu-Ping CHIANG
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Publication number: 20220152069Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Applicant: SyneuRx International (Taiwan) Corp.Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
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Publication number: 20220139452Abstract: A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.Type: ApplicationFiled: November 30, 2020Publication date: May 5, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC Nanjing Company Limited, TSMC China Company LimitedInventors: Xiu-Li YANG, He-Zhou WAN, Lu-Ping KONG, Wei-Yang JIANG
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Patent number: 11289612Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.Type: GrantFiled: March 19, 2020Date of Patent: March 29, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Cheng-Ta Yang, Lu-Ping Chiang