Patents by Inventor Lu PING

Lu PING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11557336
    Abstract: A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 17, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Lu-Ping Kong, Wei-Yang Jiang
  • Patent number: 11492546
    Abstract: Herein are described two-dimensional metal organic frameworks (2D MOFs). The 2D MOFs includes a plurality of multivalent metals or metal ions and a plurality of multidentate ligands arranged to form a crystalline structure having a lateral size of at least about 2.5 ?m and a thickness of less than about 5 nm. Herein are also described methods for preparing the 2D MOFs. The 2D MOFs can be used, for example, in electrochromic devices such as smart windows and flexible displays.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 8, 2022
    Assignee: TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Xi Ling, Ran Li, Lu Ping
  • Publication number: 20220335992
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
  • Patent number: 11398261
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 26, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
  • Publication number: 20220218730
    Abstract: A compound of Formula (I): or a pharmaceutically acceptable salt thereof, in which Ring X is a 3 to 7 membered monocyclic ring, at least one of R1, R2, R3, and R4 is OR5 or CH2OR5 and the other R1, R2, R3, and R4 each independently are halogen, OH, OR5, CH2OR5, CO2H, OC?OR6, (C?O)R6, R6, C1-10 alkyl, C2-10 alkenyl, C2-10 alkynyl, H, or absent. Also provided herein are therapeutic uses of the compound of Formula (I).
    Type: Application
    Filed: March 21, 2022
    Publication date: July 14, 2022
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Patent number: 11382924
    Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: July 12, 2022
    Assignee: SyneuRx International (Taiwan) Corp.
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Publication number: 20220189541
    Abstract: A circuit includes a tracking word line, a power switch, a tracking bit line, a sense circuit. The power switch is coupled between the tracking word line and a first node. The power switch is configured to discharge a voltage level on the first node in response to a clock pulse signal transmitted through the tracking word line to the power switch. The tracking bit line is coupled between the first node and a plurality of tracking cells in a memory array. The sense circuit is coupled between the first node and a second node. The sense circuit is configured to generate a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 16, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, Lu-Ping KONG, Kuan CHENG, He-Zhou WAN
  • Publication number: 20220165315
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Application
    Filed: January 25, 2021
    Publication date: May 26, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
  • Publication number: 20220157993
    Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 19, 2022
    Inventors: Cheng-Ta YANG, Lu-Ping CHIANG
  • Publication number: 20220152069
    Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: SyneuRx International (Taiwan) Corp.
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Publication number: 20220139452
    Abstract: A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.
    Type: Application
    Filed: November 30, 2020
    Publication date: May 5, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, He-Zhou WAN, Lu-Ping KONG, Wei-Yang JIANG
  • Patent number: 11289612
    Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: March 29, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Cheng-Ta Yang, Lu-Ping Chiang
  • Publication number: 20220054516
    Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: July 16, 2021
    Publication date: February 24, 2022
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Publication number: 20220022540
    Abstract: An electronic cigarette structure includes a casing having an e-liquid chamber and an opening in communication therewith, a cotton body, an airflow duct, an atomizer, and a cover on the opening and sealing the components above in the chamber. The cotton body is disposed in the e-liquid chamber for absorbing the e-liquid. The airflow duct is hollow and combined into the cotton body in the e-liquid chamber. The atomizer is disposed in the through hole of the airflow duct, so as to thermally atomize the e-liquid for producing smoke. The cover has a via hole in communication with the through hole, so that the smoke generated in the through hole is sucked out from the via hole. Thus, the tar separation is avoided, and the e-liquid is prevented from leaking.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: WEI-SHIN WEI, BI-HONG CHI, LU-PING JIAO
  • Patent number: 11154531
    Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: October 26, 2021
    Assignee: SYNEURX INTERNATIONAL (TAIWAN) CORP.
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Publication number: 20210251945
    Abstract: A method of treating coronavirus infection, comprising administering to a subject in need thereof an effective amount of a composition, wherein the composition comprises one or more compounds of Formula (I): or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: September 8, 2020
    Publication date: August 19, 2021
    Inventors: Guochuan Emil Tsai, Yi-Wen Mao, Lu-Ping Lu, Wei-Hua Chang, Han-Yi Hsieh, Jhe Wei Hu, Tsai-Miao Shih, ChanHui Huang
  • Publication number: 20210122775
    Abstract: Herein are described two-dimensional metal organic frameworks (2D MOFs). The 2D MOFs includes a plurality of multivalent metals or metal ions and a plurality of multidentate ligands arranged to form a crystalline structure having a lateral size of at least about 2.5 ?m and a thickness of less than about 5 nm. Herein are also described methods for preparing the 2D MOFs. The 2D MOFs can be used, for example, in electrochromic devices such as smart windows and flexible displays.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Applicant: TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Xi LING, Ran LI, Lu PING
  • Patent number: 10847612
    Abstract: A method of manufacturing a memory structure including the following steps is provided. Stacked structures are formed on a substrate, and each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structure, and the first opening extends into the substrate. At least one isolation structure is formed in the first opening. The isolation structure covers a sidewall of the first dielectric layer. The isolation structure has a recess therein, such that a top profile of the isolation structure is shaped as a funnel. A second dielectric layer is formed on the stacked structures. A second conductive layer is formed on the second dielectric layer and fills the first opening.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 24, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
  • Publication number: 20200303556
    Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 24, 2020
    Inventors: Cheng-Ta YANG, Lu-Ping CHIANG
  • Patent number: 10566337
    Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: February 18, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang