Patents by Inventor Lu Yi
Lu Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10128178Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.Type: GrantFiled: September 7, 2016Date of Patent: November 13, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Hung-Yuan Li, Chieh-Lung Lai, Shih-Liang Peng, Chang-Lun Lu
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Publication number: 20180261563Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.Type: ApplicationFiled: May 9, 2018Publication date: September 13, 2018Inventor: Lu-Yi Chen
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Publication number: 20180254227Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 9997481Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.Type: GrantFiled: September 27, 2012Date of Patent: June 12, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventor: Lu-Yi Chen
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Patent number: 9991178Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: GrantFiled: September 14, 2012Date of Patent: June 5, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20180047610Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.Type: ApplicationFiled: October 11, 2017Publication date: February 15, 2018Inventors: Lu-Yi Chen, Chang-Lun Lu
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Publication number: 20180042112Abstract: An electronic device includes a circuit board having a plurality of conductive contacts, and an electronic component disposed on the circuit board and having a plurality of electrode terminals. The conductive contacts include a plurality of solder pads spaced apart from each other, and are coupled to the electrode terminals, respectively. The stress generated by any one of the electrode terminals is distributed to all of the solder pads so as to prevent the electronic component from being offset during an assembly process.Type: ApplicationFiled: October 17, 2016Publication date: February 8, 2018Inventors: Lu-Yi Chen, Cheng-Hsiang Liu, Chang-Lun Lu, Jun-Cheng Liao, Cheng-Yi Chen
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Publication number: 20170338173Abstract: An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.Type: ApplicationFiled: September 7, 2016Publication date: November 23, 2017Inventors: Lu-Yi Chen, Hung-Yuan Li, Chieh-Lung Lai, Shih-Liang Peng, Chang-Lun Lu
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Patent number: 9818635Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.Type: GrantFiled: December 29, 2015Date of Patent: November 14, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chang-Lun Lu
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Publication number: 20170309534Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.Type: ApplicationFiled: July 11, 2017Publication date: October 26, 2017Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen
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Patent number: 9735075Abstract: An electronic module is provided, including an electronic element and a strengthening layer formed on a side surface of the electronic element but not formed on an active surface of the electronic element so as to strengthen the structure of the electronic module. Therefore, the electronic element is prevented from being damaged when the electronic module is picked and placed.Type: GrantFiled: October 16, 2014Date of Patent: August 15, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen
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Publication number: 20170148761Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.Type: ApplicationFiled: January 6, 2017Publication date: May 25, 2017Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
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Patent number: 9601403Abstract: An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.Type: GrantFiled: December 29, 2015Date of Patent: March 21, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Guang-Hwa Ma, Shih-Ching Chen, Chang-Lun Lu
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Publication number: 20170047262Abstract: An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.Type: ApplicationFiled: December 29, 2015Publication date: February 16, 2017Inventors: Lu-Yi Chen, Guang-Hwa Ma, Shih-Ching Chen, Chang-Lun Lu
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Publication number: 20170033027Abstract: An electronic package is provided, including: a circuit structure having opposite first and second surfaces, wherein first and second circuit layers are formed on the first and second surfaces of the circuit structure, respectively, the first circuit layer having a minimum trace width less than that of the second circuit layer; a separation layer formed on the first surface of the circuit structure; a metal layer formed on the separation layer and electrically connected to the first circuit layer; an electronic element disposed on the first surface of the circuit structure and electrically connected to the metal layer; and an encapsulant formed on the circuit structure to encapsulate the electronic element. By disposing the electronic element having high I/O function on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package.Type: ApplicationFiled: December 29, 2015Publication date: February 2, 2017Inventors: Lu-Yi Chen, Chang-Lun Lu
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Publication number: 20170005023Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.Type: ApplicationFiled: January 27, 2016Publication date: January 5, 2017Inventors: Lu-Yi Chen, Chang-Lun Lu
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Patent number: 9515039Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.Type: GrantFiled: December 30, 2015Date of Patent: December 6, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Lu-Yi Chen, Yu-Chuan Chen, Chang-Lun Lu
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Publication number: 20160322323Abstract: A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.Type: ApplicationFiled: December 30, 2015Publication date: November 3, 2016Inventors: Chieh-Lung Lai, Lu-Yi Chen, Yu-Chuan Chen, Chang-Lun Lu
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Patent number: D802515Type: GrantFiled: October 21, 2016Date of Patent: November 14, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Lu Yi, Masayuki Sugiura, Masahiko Nakamura, Yoshikiyo Ichino
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Patent number: D812543Type: GrantFiled: October 21, 2016Date of Patent: March 13, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Lu Yi, Masayuki Sugiura, Masahiko Nakamura