Abstract: Embodiments of the present disclosure provide for methods that can be used to produce carbon nanotubes (hereinafter CNT) having an inner diameter about 5-55 nm, methods of tuning the inner diameter of CNTs (e.g., by adjusting reaction pressure), CNTs having an inner diameter of greater than 20 nm or more, and the like.

Abstract: 2-alkoxy benzene formyl arylamine compounds and their pharmaceutical salts are disclosed. The compounds can act as sphingomyelin synthase (SMS) inhibitors to treat diseases caused by abnormal increasing of sphingomyelin (SM). The pharmaceutically acceptable salts and pharmaceutical compositions of the compounds are used as active ingredients in drugs which can prevent and cure diseases caused by SM level abnormal increase. These diseases include atherosclerosis, fatty liver, obesity, type diabetes, and other metabolic syndromes.

Abstract: A preparation method for extractive botanicals includes: (A) honeysuckle, schizonepeta, and purslane in a powder are mixed, ground, and passed through a mesh; the medicinal powder obtained from supercritical extraction is soaked in alcohol, then undergoes percolation extraction, and the percolate is collected; (B) the alcohol percolate is concentrated, left stand, and suction filtrated to obtain a filtrate; (C) the filtrate macroporously adsorbs to a resin column at a flow velocity, is then removed of impurity by water washing, and undergoes elution with alcohol to obtain an alcohol eluent; (D) alcohol is recovered from the eluent, the remaining liquid is concentrated, and the concentrated liquid is dried to obtain the extractive of botanicals. The total content of flavones, saponins, and organic acids exceeds 70%. The extractive has substantial anti-inflammatory and pain relieving effects.

Abstract: A system for preparing nanoparticles by supercritical hydrothermal synthesis is provided. Firstly, a mixture of a first reactant and a second reactant and high-temperature water at an outlet of a heating furnace (10) are mixed and are heated to a reaction temperature, the mixture is connected to a supercritical hydrothermal synthesis reactor (14), and a product at an outlet of the supercritical hydrothermal synthesis reactor enters a heat regenerator (9); hot water at an outlet of a low-temperature section of the heating furnace (10) first enters the heat regenerator, and then enters a high-temperature section of the heating furnace so as to be continuously heated to a set temperature; fluid at the pipe side outlet of the heat regenerator separately passes through a heat exchange coil in a first reactant modulation pool (1) and a steam generator (2) in a waste heat power generation system (20).

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: Embodiments of the present disclosure provide for supported Ni/Pt bimetallic nanoparticles having a Ni core and a Pt layer disposed on the surface of the Ni core, compositions including supported NiPt nanoparticles, methods of making supported NiPt nanoparticles, methods of using supported NiPt nanoparticles, and the like.

Abstract: Embodiments of the present disclosure also provide for a supported fused Fe catalyst, a method of making the supported fused Fe catalyst, methods of hydrocarbon decomposition, and the like.

Abstract: Polypeptides comprising high affinity for the uranyl ion are provided. Methods for binding uranyl using such proteins are likewise provided and can be used, for example, in methods for uranium purification or removal.

Abstract: A method for controlling desalination and salt discharging in a supercritical water oxidation system includes a step of providing a system including a heating furnace (1), a hydrocyclone (2), a buffer oxidizer (3), a flash tank (4) and related control valves. The method further includes a step of controlling desalination and salt discharging: discharging salts from the hydrocyclone (2) into the buffer oxidizer (3); discharging the salts from the buffer oxidizer (3) into the flash tank (4), in an intermittent automatic operation manner The method accomplishes an efficient and continuous desalination of the organic waste supercritical water oxidation treatment system, via storing the salts by the salt storage buffer tank under the hydrocyclone (2) and the buffer oxidizer (3).

Abstract: Polypeptides comprising high affinity for the uranyl ion are provided. Methods for binding uranyl using such proteins are likewise provided and can be used, for example, in methods for uranium purification or removal.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: A countercurrent tank type supercritical water reactor with a sacrificial lining, comprising a cylinder body and a catalyst tank arranged inside, the upper part of the cylinder body is connected with a top cover, and the lower part of the cylinder body is connected with a spherical head, the inner side of the cylinder body, the inner side of the spherical head and the inner side of the top cover constitute the inner wall of the reactor, wherein the inner wall of the reactor is provided with a high temperature resistance and thermal insulation coating layer, the inner wall of the high temperature resistance and thermal insulation coating layer is provided with a sealing coating layer, and the inner wall of the sealing coating layer is provided with the sacrificial lining. The reactor is of a countercurrent tank type, which can prevent the reactor blockage caused by salt deposition.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

Abstract: The present invention discloses a preparation method for extractive of Jinxuan Hemorrhoid Washing Powder botanicals comprises the steps: A, honeysuckle, schizonepeta, and purslane in the prescription of Jinxuan Hemorrhoid Washing Powder are mixed, ground, and passed through a mesh; the medicinal powder obtained from supercritical extraction is soaked in alcohol, then undergoes percolation extraction, and the percolate is collected; B, the alcohol percolate is concentrated, left stand, and suction filtrated to obtain a filtrate; C, the filtrate macroporously adsorpts to a resin column at a flow velocity, is then removed of to impurity by water washing, and undergoes elution with alcohol to obtain an alcohol eluent; D, alcohol is recovered from the eluent, the remaining liquid is concentrated, and the concentrated liquid is dried to obtain the extractive of Jinxuan Hemorrhoid Washing Powder botanicals.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. If the mode flag indicates a design state, the configuration logic associated with the logic block is included in data verification and correction processes. If the mode flag indicates a user defined state, the configuration logic associated with the logic block is excluded from data verification and correction processes. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state without causing deleterious effects.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.