Abstract: Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2N memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: There are provided methods and devices for providing overdrive voltages to address lines to help prevent leakage current in semiconductor memories, such as configuration memories used with programmable logic devices. Specifically, for example, there is provided a memory that includes an array of memory cells. Each memory cell includes a retainer circuit. An access transistor is coupled to the retainer circuit. An overdrive voltage level may be applied to the access transistor.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

Abstract: An electrical device includes a thermistor and at least two electrodes electrically connected to the thermistor and to which a source of electrical power is applied to cause current to flow through the thermistor. The thermistor may be a composite and includes a polymer material; and a plurality of conductive carbon nanotubes distributed in the polymer material. The electrical device employed with the thermistor performs not only PTC property, but also NTC property. Moreover, the method for fabricating the electrical device is also simple and easy to carry out because of the simple process.

Abstract: Exemplary systems and methods are provided by which multiple persons in remote physical locations can collaboratively interactively visualize a 3D data set substantially simultaneously. In exemplary embodiments of the present invention, there can be, for example, a main workstation and one or more remote workstations connected via a data network. A given main workstation can be, for example, an augmented reality surgical navigation system, or a 3D visualization system, and each workstation can have the same 3D data set loaded. Additionally, a given workstation can combine real-time imagining with previously obtained 3D data, such as, for example, real-time or pre-recorded video, or information such as that provided by a managed 3D ultrasound visualization system.