Patents by Inventor Luigi Capodieci
Luigi Capodieci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6978438Abstract: A method and associated computer program for making optical proximity corrections for a reticle layout topology. Edge segments of the reticle layout topology are manipulated to generate a corrected reticle layout accounting for optical distortions and, based on the corrected reticle layout, a plurality of individual figure of merit values are generated. A generalized figure of merit (GFOM) using the plurality of individual figure of merit values is then generated.Type: GrantFiled: October 1, 2003Date of Patent: December 20, 2005Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6974652Abstract: A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.Type: GrantFiled: November 3, 2003Date of Patent: December 13, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Todd P. Lukanc, Luigi Capodieci, Bhanwar Singh, Christopher A. Spence
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Publication number: 20050243299Abstract: A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.Type: ApplicationFiled: April 28, 2004Publication date: November 3, 2005Inventors: Christopher Spence, Todd Lukanc, Luigi Capodieci, Joerg Reiss, Sarah McGowan
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Publication number: 20050229125Abstract: A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).Type: ApplicationFiled: April 2, 2004Publication date: October 13, 2005Inventors: Cyrus Tabery, Todd Lukanc, Chris Haidinyak, Luigi Capodieci, Carl Babcock, Hung-eil Kim, Christopher Spence
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Patent number: 6583041Abstract: A method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate layer over the first portion of the microdevice component; forming a second regular array of lines and spaces from a second layer of material deposited on the intermediate layer; patterning the second regular array of lines and spaces to form a second portion of the microdevice component; and forming contact holes in the intermediate layer to establish conductivity between the first portion of the microdevice component and the second portion of the microdevice component.Type: GrantFiled: May 1, 2000Date of Patent: June 24, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6562639Abstract: In order to determine an amount of critical dimension variation to expect across a surface of a final production wafer, a plurality of test structures are formed on a test wafer. The test structures are preferably of a type commonly found on the final production wafer and may for example, include transistors, ring oscillators, resistors and/or diodes. Electrical parameter testing of the test structures is next conducted in order to obtain one or more electrical performance values for each test structure. For example, the electrical performance values may correspond to processing speed, drive current, and/or off-state current of the test structures. A correlation between the electrical performance values and expected critical dimension variations is then performed and a report is generated providing the expected critical dimension variations across the surface of the wafer.Type: GrantFiled: November 6, 2001Date of Patent: May 13, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Anna Minvielle, Luigi Capodieci, Christopher Spence
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Patent number: 6553562Abstract: A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying “horizontal” critical features and “vertical” critical features from a plurality of features forming a layout; identifying interconnection areas which are areas in which one of the horizontal critical features or the vertical critical features contacts another feature of the layout; defining a set of primary parameters on the basis of the proximity of the plurality of features relative to one another; and generating an edge modification plan for each interconnection area based on the primary parameters. A horizontal mask pattern is then generated by compiling the horizontal critical features, a first shield plan for the vertical critical features and the interconnection areas containing a horizontal critical feature modified by the edge modification plan.Type: GrantFiled: November 5, 2001Date of Patent: April 22, 2003Assignees: ASML Masktools B.V., ASM Lithography B.V.Inventors: Luigi Capodieci, Juan Andres Torres Robles, Lodewijk Hubertus Van Os
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Patent number: 6492066Abstract: A method (100) of characterizing optical proximity correction designs includes performing a mathematical transform (160) on a first feature (150) and a second feature (167) each having a core portion (152) and a first OPC design and a second OPC design applied thereto, respectively. The method (100) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features (150, 167) as a patterns thereon. One of the first feature or the second feature is then selected (170) based upon an application of the metric to the first and second transformed features (150, 167), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.Type: GrantFiled: May 28, 1999Date of Patent: December 10, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Luigi Capodieci, Christopher A. Spence
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Publication number: 20020166107Abstract: A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying “horizontal” critical features and “vertical” critical features from a plurality of features forming a layout; identifying interconnection areas which are areas in which one of the horizontal critical features or the vertical critical features contacts another feature of the layout; defining a set of primary parameters on the basis of the proximity of the plurality of features relative to one another; and generating an edge modification plan for each interconnection area based on the primary parameters. A horizontal mask pattern is then generated by compiling the horizontal critical features, a first shield plan for the vertical critical features and the interconnection areas containing a horizontal critical feature modified by the edge modification plan.Type: ApplicationFiled: November 5, 2001Publication date: November 7, 2002Inventors: Luigi Capodieci, Juan Andres Torres Robles, Lodewijk Hubertus Van Os
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Patent number: 6458606Abstract: Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.Type: GrantFiled: May 11, 2001Date of Patent: October 1, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Marina V. Plat, Luigi Capodieci, Scott A. Bell, Todd Lukanc
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Publication number: 20010031506Abstract: Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.Type: ApplicationFiled: May 11, 2001Publication date: October 18, 2001Inventors: Marina V. Plat, Luigi Capodieci, Scott A. Bell, Todd Lukanc
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Patent number: 6272392Abstract: A method (250) of extracting effective imaging system aberrations from test data collected from test structures (220) constructed from a lithography system having an imaging system associated therewith includes inputting (264) experimental critical dimension data corresponding to fabricated features (220) on a substrate (212) to a neural network (208). The method (250) also includes inputting (266) nominal critical dimension data corresponding to the fabricated features on the substrate (212) to the neural network (208) and determining (268) the effective aberrations of the imaging system associated with the lithography system used to fabricate the features (220) using the neural network (208).Type: GrantFiled: December 4, 1998Date of Patent: August 7, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6262435Abstract: Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.Type: GrantFiled: December 1, 1998Date of Patent: July 17, 2001Inventors: Marina V. Plat, Luigi Capodieci, Scott A. Bell, Todd Lukanc
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Patent number: 6187483Abstract: A method (200) of determining an optimal mask fabrication process includes fabricating (202) a first mask pattern (220) on a mask using a first mask fabrication process and a second mask pattern (222) on a mask using a second mask fabrication process, wherein each mask pattern approximates an ideal pattern. The method (200) further includes performing a mathematical transform on the first and second mask patterns (230), wherein the mathematical transform provides a representation of the first and second mask patterns as sums of functions.Type: GrantFiled: May 28, 1999Date of Patent: February 13, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Luigi Capodieci, Christopher A. Spence
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Patent number: 6115108Abstract: A method (400) of determining a custom illumination scheme for a projection-type photolithography system (500) is disclosed. The custom illumination scheme provides compensation for imaging system aberrations within the photolithography system (500) and thereby reduces critical dimension non-uniformities of features produced by the photolithography system (500) across a substrate (120). The method (400) includes the steps of performing a lithography simulation (404) for one or more nominal features using imaging system aberration data which characterizes the photolithography system (500) and an initial illumination scheme. The lithography simulation includes one or more simulated features which differ from the one or more nominal features due to the imaging system aberration data.Type: GrantFiled: December 4, 1998Date of Patent: September 5, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6044007Abstract: A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner which provides for improved writeability of OPC independent of process push or bias. Alternatively, the data storage medium contains mask layout data which includes a second mask data portion. The second mask data portion corresponds to a feature having an exterior corner and includes a multi-level or stepped outer serif on the exterior corner. The stepped outer serif also provides for improved writeability of OPC independent of process push or bias.Type: GrantFiled: March 24, 1999Date of Patent: March 28, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6040118Abstract: A method (100) of providing critical dimension uniformity in a radiation sensitive film (104) includes the steps of forming (102) the radiation sensitive film (104) over a substrate (106) and exposing (110) the radiation sensitive film (104) to radiation (56) using a mask (50) having a pattern thereon, wherein a first feature (52) and a second feature (54) on the mask (50) are intended to provide the same critical dimension on the radiation sensitive film (104). The exposure step (110) creates a non-uniform exposure pattern (60) on the radiation sensitive film (104) corresponding to the mask pattern due to various anomalies in the exposure process or in the mask itself. A transferred first feature (84) critical dimension on the radiation sensitive film (104) which corresponds to the first mask feature (52) is larger than the second transferred feature (86) critical dimension which corresponds to the second mask feature (54) due to the radiation non-uniformities or imaging non-uniformities.Type: GrantFiled: October 30, 1998Date of Patent: March 21, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6037082Abstract: A mask (50) for use in lithographic printing includes a pattern (54) formed of a material which is substantially opaque with respect to a wavelength of radiation being used in the lithographic printing. The pattern (54) on the mask (50) corresponds to a desired feature to be formed on a substrate and includes a grating (58) having an alternating pattern of opaque and transparent regions (60, 62). The alternating pattern provides destructive interference of radiation at the substrate in a region corresponding to the desired feature due to diffraction, thereby improving resolution at the substrate. In addition, the alternating pattern (60, 62) on the mask (50) increases a number of focal planes at which the destructive interference occurs and thereby improves a focus process latitude by providing an acceptable resolution over variations in a distance between the mask (50) and the substrate.Type: GrantFiled: October 30, 1998Date of Patent: March 14, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 6013396Abstract: A mask (50) for use in lithographic printing includes a pattern (54) formed of a material which is substantially opaque with respect to a wavelength of radiation being used in the lithographic printing. The pattern (54) on the mask (50) corresponds to a desired feature to be formed on a substrate and includes a grating (58) having an alternating pattern of opaque and transparent regions (60, 62). The alternating pattern provides destructive interference of radiation at the substrate in a region corresponding to the desired feature due to diffraction, thereby improving resolution at the substrate. In addition, the alternating pattern (60, 62) on the mask (50) increases a number of focal planes at which the destructive interference occurs and thereby improves a focus process latitude by providing an acceptable resolution over variations in a distance between the mask (50) and the substrate.Type: GrantFiled: October 30, 1998Date of Patent: January 11, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci
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Patent number: 5717612Abstract: A system that simulates the physics of chemically amplified photoresist during bake processing after X-ray or ultraviolet exposure and before development. The simulator implements a physical model including both kinetic reaction between photoacid and tBOC, and photoacid diffusion. The simulator is supplied with initial post-exposure bake parameters, for example, PEB time and temperature, selected for baking a particular photoresist. Data for implementing the physical model at the selected PEB time and temperature are established experimentally and supplied to the PEB simulator to determine the photoacid concentration in the photoresist. The tBOC concentration is calculated using the value of the photoacid concentration.Type: GrantFiled: June 6, 1995Date of Patent: February 10, 1998Assignee: Advanced Micro Devices, Inc.Inventor: Luigi Capodieci