Patents by Inventor Luigi Colombo

Luigi Colombo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Control of high-k gate dielectric film composition profile for property optimization
    Patent number: 7071519
    Abstract: Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: July 4, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, Mark Visokay, James Joseph Chambers, Antonio Luis Pacheco Rotondaro
  • Gate dielectric and method
    Publication number: 20060138556
    Abstract: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.
    Type: Application
    Filed: January 25, 2006
    Publication date: June 29, 2006
    Inventors: Mark Visokay, Antonio Rotondaro, Luigi Colombo
  • Hydrogen free integration of high-k gate dielectrics
    Patent number: 7067434
    Abstract: The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Mark R. Visokay
  • Top surface roughness reduction of high-k dielectric materials using plasma based processes
    Publication number: 20060121744
    Abstract: A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
    Type: Application
    Filed: January 5, 2006
    Publication date: June 8, 2006
    Inventors: Manuel Quevedo-Lopez, James Chambers, Luigi Colombo, Mark Visokay
  • Method for integrating high-k dielectrics in transistor devices
    Patent number: 7045431
    Abstract: Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Douglas E. Mercer, Luigi Colombo, Mark Robert Visokay, Haowen Bu, Malcolm John Bevan
  • MOS transistor gates with thin lower metal silicide and methods for making the same
    Patent number: 7045456
    Abstract: Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Robert William Murto, Luigi Colombo, Mark Robert Visokay
  • Dalbavancin compositions for treatment of bacterial infections
    Publication number: 20060074014
    Abstract: The invention provides methods and compositions for treatment of bacterial infections. The composition may be a combination of factors, which include A0, A1, B1, B2, C0, C1, isoB0, and MAG, in the presence of low level solvent. Methods of the invention include administration of dalbavancin formulations for treatment of a bacterial infection, in particular a Gram-positive bacterial infection of skin and soft tissue. Dosing regimens include multiple dose administration of dalbavancin, which often remains at therapeutic levels in the bloodstream for at least one week, providing prolonged therapeutic action against a bacterial infection. Dosing regimens for renal patients are also included.
    Type: Application
    Filed: April 26, 2005
    Publication date: April 6, 2006
    Applicant: VICURON PHARMACEUTICALS INC.
    Inventors: Martin Stogniew, Luigi Colombo, Romeo Ciabatti
  • Gate dielectric and method
    Patent number: 7018902
    Abstract: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: March 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Mark R. Visokay, Antonio L. P. Rotondaro, Luigi Colombo
  • High-K gate dielectric defect gettering using dopants
    Patent number: 7015088
    Abstract: One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Antonio Luis Pacheco Rotondaro
  • Encapsulated MOS transistor gate structures and methods for making the same
    Patent number: 7015534
    Abstract: Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by nitriding the sidewalls of the gate structure, and a silicon nitride encapsulation layer is formed to protect the conditioned sidewalls during manufacturing processing. The conditioning and encapsulation avoid oxidation of gate stack layers, particularly metal gate layers, and also facilitate repairing or restoring stoichiometry of metal and other gate layers that may be damaged or altered during gate patterning.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: March 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Luigi Colombo
  • Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
    Publication number: 20060040483
    Abstract: A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a nitrogen-containing gas, where the process gas pressure is selected to control the amount of neutral radicals relative to the amount of ionic radicals in the plasma, and modifying the gate dielectric stack by exposing the stack to the plasma.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 23, 2006
    Inventors: Hiroaki Niimi, Luigi Colombo, Koji Shimomura, Takuya Sugawara, Tatsuo Matsudo
  • Dual work function gate electrodes obtained through local thickness-limited silicidation
    Publication number: 20060019437
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.
    Type: Application
    Filed: July 23, 2004
    Publication date: January 26, 2006
    Applicant: Texas Instruments, Incorporated
    Inventors: Robert Murto, Luigi Colombo, Mark Visokay
  • Method for fabricating split gate transistor device having high-k dielectrics
    Patent number: 6979623
    Abstract: Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: December 27, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Mark Robert Visokay, James J. Chambers, Luigi Colombo
  • Dual work function metal gate integration in semiconductor devices
    Publication number: 20050258468
    Abstract: The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
    Type: Application
    Filed: July 13, 2004
    Publication date: November 24, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Luigi Colombo, James Chambers, Mark Visokay
  • Refractory metal-based electrodes for work function setting in semiconductor devices
    Publication number: 20050258500
    Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
    Type: Application
    Filed: May 24, 2004
    Publication date: November 24, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Luigi Colombo, James Chambers, Mark Visokay
  • Semiconductor device having multiple work functions and method of manufacture therefor
    Publication number: 20050233533
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.
    Type: Application
    Filed: April 16, 2004
    Publication date: October 20, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Husam Alshareef, Mark Visokay, Antonio Rotondaro, Luigi Colombo
  • Integrated circuit and method
    Publication number: 20050227378
    Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
    Type: Application
    Filed: June 6, 2005
    Publication date: October 13, 2005
    Inventors: Theodore Moise, Guoqiang Xing, Mark Visokay, Justin Gaynor, Stephen Gilbert, Francis Celii, Scott Summerfelt, Luigi Colombo
  • Gate dielectric and method
    Publication number: 20050205948
    Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 22, 2005
    Inventors: Antonio Rotondaro, Luigi Colombo, Malcolm Bevan
  • Metal gate MOS transistors and methods for making the same
    Patent number: 6936508
    Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: August 30, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Visokay, Luigi Colombo, James J. Chambers
  • Gate dielectric and method
    Patent number: 6919251
    Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 19, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Luigi Colombo, Malcolm J. Bevan