Patents by Inventor Luigi Colombo

Luigi Colombo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual work function CMOS devices utilizing carbide based electrodes
    Publication number: 20070037335
    Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 15, 2007
    Inventors: James Chambers, Luigi Colombo, Mark Visokay
  • Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
    Patent number: 7176076
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: February 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Mark Robert Visokay, Luigi Colombo
  • Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
    Patent number: 7163877
    Abstract: A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a nitrogen-containing gas, where the process gas pressure is selected to control the amount of neutral radicals relative to the amount of ionic radicals in the plasma, and modifying the gate dielectric stack by exposing the stack to the plasma.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: January 16, 2007
    Assignees: Tokyo Electron Limited, Texas Instruments, Inc.
    Inventors: Hiroaki Niimi, Luigi Colombo, Koji Shimomura, Takuya Sugawara, Tatsuo Matsudo
  • DUAL WORK FUNCTION GATE ELECTRODES USING DOPED POLYSILICON AND A METAL SILICON GERMANIUM COMPOUND
    Publication number: 20060292790
    Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
    Type: Application
    Filed: August 8, 2006
    Publication date: December 28, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antonio Rotondaro, Mark Visokay, Luigi Colombo
  • MOS transistor gates with doped silicide and methods for making the same
    Patent number: 7148546
    Abstract: Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Visokay, Luigi Colombo
  • REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES
    Publication number: 20060273414
    Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
    Type: Application
    Filed: August 17, 2006
    Publication date: December 7, 2006
    Inventors: Luigi Colombo, James Chambers, Mark Visokay
  • REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES
    Publication number: 20060267119
    Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: Luigi Colombo, James Chambers, Mark Visokay
  • Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows
    Publication number: 20060258074
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that form metal silicide gates and mitigate formation of silicide region defects near channel regions. A dielectric layer is formed over a semiconductor device (306). Polysilicon is deposited on the dielectric layer to form a gate electrode layer (308) and a patterning operation is then performed to form gate structures (310). Source/drain regions are formed (320) and the gate structures are tuned to obtain a selected work function (324). A metal is then selectively deposited on only the gate structures (328) and a thermal process is performed that reacts the deposited metal with polysilicon of the gate layer to obtain a metal suicide material (330).
    Type: Application
    Filed: May 12, 2005
    Publication date: November 16, 2006
    Inventors: Mark Visokay, James Chambers, Luigi Colombo
  • Method for fabricating transistor gate structures and gate dielectrics thereof
    Patent number: 7135361
    Abstract: Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: November 14, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Mark R. Visokay, Luigi Colombo, James J. Chambers, Antonio L. P. Rotondaro, Haowen Bu
  • MOS Transistor Gates with Doped Silicide and Methods for Making the Same
    Publication number: 20060244045
    Abstract: Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.
    Type: Application
    Filed: July 13, 2006
    Publication date: November 2, 2006
    Inventors: Mark Visokay, Luigi Colombo
  • Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation
    Publication number: 20060246716
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. A first oxide layer is formed in core and I/O regions of a semiconductor device (506). The first oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A second oxide layer is formed (516) within NMOS regions of the core and I/O regions and a nitridation process is performed (518) that nitrides the second oxide layer and the high-k dielectric layer.
    Type: Application
    Filed: April 29, 2005
    Publication date: November 2, 2006
    Inventors: Luigi Colombo, James Chambers, Mark Visokay
  • Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon
    Publication number: 20060246647
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.
    Type: Application
    Filed: April 29, 2005
    Publication date: November 2, 2006
    Inventors: Mark Visokay, Luigi Colombo, James Chambers
  • Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials
    Publication number: 20060246651
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
    Type: Application
    Filed: April 29, 2005
    Publication date: November 2, 2006
    Inventors: James Chambers, Mark Visokay, Luigi Colombo
  • Top surface roughness reduction of high-k dielectric materials using plasma based processes
    Patent number: 7115530
    Abstract: A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: October 3, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Manuel A. Quevedo-Lopez, James J. Chambers, Luigi Colombo, Mark R. Visokay
  • Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound
    Patent number: 7109077
    Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: September 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio L. P. Rotondaro, Mark R. Visokay, Luigi Colombo
  • Semiconductor structure and method of fabrication
    Publication number: 20060202300
    Abstract: Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.
    Type: Application
    Filed: March 30, 2006
    Publication date: September 14, 2006
    Inventors: Mark Visokay, Luigi Colombo
  • Gate structure and method
    Patent number: 7105891
    Abstract: CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: September 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Mark R. Visokay, Antonio L. P. Rotondaro, Luigi Colombo
  • Refractory metal-based electrodes for work function setting in semiconductor devices
    Patent number: 7098516
    Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James J. Chambers, Mark R. Visokay
  • Encapsulated MOS transistor gate structures and methods for making the same
    Patent number: 7091119
    Abstract: Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by nitriding the sidewalls of the gate structure, and a silicon nitride encapsulation layer is formed to protect the conditioned sidewalls during manufacturing processing. The conditioning and encapsulation avoid oxidation of gate stack layers, particularly metal gate layers, and also facilitate repairing or restoring stoichiometry of metal and other gate layers that may be damaged or altered during gate patterning.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: August 15, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Luigi Colombo
  • Control of high-k gate dielectric film composition profile for property optimization
    Patent number: 7071519
    Abstract: Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: July 4, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Luigi Colombo, Mark Visokay, James Joseph Chambers, Antonio Luis Pacheco Rotondaro