Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described.

Abstract: An amplification system for reducing DC offset in an input signal uses a low pass filter to isolate a DC component of the input signal. The system then subtracts the DC component from the input signal. In one embodiment, the system includes first and second amplifiers in addition to the low pass filter. The first amplifier amplifies the input signal to generate a first amplified signal at a differential output port of the amplification system. The second amplifier amplifies a low pass filtered version of the input signal to generate a second amplified signal at the differential output port of the amplification system. The outputs of the first and second amplifiers are connected to the differential output port of the amplification system in such a way that the first and second signals combine 180 degrees out of phase at the output port.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A transceiver system on a single package provides an RF/Microwave subsystem in an area external to the processor die which contains a digital processor. The external area may include an antenna-switch, an input matching network and an impedance transformer impedance transformer and RF-choke for a power amplifier as the passive elements to provide both lower noise reception and higher efficiency transmission.

Abstract: A high speed data bus for use within a computer system includes a plurality of interface units distributed along a bi-directional transmission medium. Each of the interface units is used to couple at least one functional unit within the computer system to the bi-directional medium. The data bus uses a non-baseband signaling scheme on the bi-directional medium to transfer data between functional units within the computer system. In one embodiment, differential small signal signaling technology is used to enable low voltage operation, power supply noise rejection, and robustness against self-inflicted jitter on the bus. The high speed data bus is preferably configured as a series of point to point communication links between adjacent interface units.

Abstract: An electrically tunable radio frequency (RF) amplifier includes a resonant circuit having a voltage variable capacitance as one of its elements. In one approach, a drain diffusion capacitance of one of the transistors within the amplifier is used as the voltage variable capacitance. A voltage adjustment unit is provided to adjust a bias voltage on the voltage variable capacitance to change the capacitance value thereof and thus modify the operating frequency range of the amplifier. In one embodiment, the voltage adjustment unit also provides a power supply noise blocking function.

Abstract: A clock signal is generated by receiving an input clock signal having an input clock signal frequency, dividing the input clock signal frequency by a selected number to produce a lower frequency output clock signal, and shifting the phase of the output clock signal. The phase can be shifted by changing, for at least a predetermined amount of time, the selected number by which the input clock signal frequency is divided, and then restoring the selected number to its original value. The clock can be used as a channel sampling clock, and it can be synchronized to the data by the phase shifting. One implementation uses a chain of flip-flops for dividing the frequency and additional circuitry for shifting phase. The flip-flops may be connected with minimum logic in order to operate at substantially the highest frequency reachable by a given transistor technology.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described. The frequency synthesizer includes two directly-connected, sequential chains of flip-flops, the first chain having N flip-flops, and the second chain having M flip-flops. The first chain of N flip-flops is clocked by a reference frequency input. Each chain provides a clocked output to an optional duty-cycle recovery circuit, which is in turn coupled to a frequency-update module. There is a sub-threshold low-pass filter included in the frequency-update module which feeds into an oscillator, providing, in turn, the generated frequency as an input to the second chain of M flip-flops, and a sub-carrier frequency output.

Abstract: A low noise microwave MOSFET fabricated with source-side halo implantation. The dopant concentration has an asymmetrical horizontal profile along the channel from the source to the drain.

Abstract: A low noise microwave MOSFET fabricated with source-side halo implantation. The dopant concentration has an asymmetrical horizontal profile along the channel from the source to the drain.

Abstract: An electrically tunable radio frequency (RF) amplifier includes a resonant circuit having a voltage variable capacitance as one of its elements. In one approach, a drain diffusion capacitance of one of the transistors within the amplifier is used as the voltage variable capacitance. A voltage adjustment unit is provided to adjust a bias voltage on the voltage variable capacitance to change the capacitance value thereof and thus modify the operating frequency range of the amplifier. In one embodiment, the voltage adjustment unit also provides a power supply noise blocking function.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described. The frequency synthesizer includes two directly-connected, sequential chains of flip-flops, the first chain having N flip-flops, and the second chain having M flip-flops. The first chain of N flip-flops is clocked by a reference frequency input. Each chain provides a clocked output to an optional duty-cycle recovery circuit, which is in turn coupled to a frequency-update module. There is a sub-threshold low-pass filter included in the frequency-update module which feeds into an oscillator, providing, in turn, the generated frequency as an input to the second chain of M flip-flops, and a sub-carrier frequency output.

Abstract: An electrically tunable radio frequency (RF) amplifier includes a resonant circuit having a voltage variable capacitance as one of its elements. In one approach, a drain diffusion capacitance of one of the transistors within the amplifier is used as the voltage variable capacitance. A voltage adjustment unit is provided to adjust a bias voltage on the voltage variable capacitance to change the capacitance value thereof and thus modify the operating frequency range of the amplifier. In one embodiment, the voltage adjustment unit also provides a power supply noise blocking function.

Abstract: A clock and data separator circuit and method that separates data and clock signals that may coincide. The separator circuits use CMOS transistors to extend the time separation between transitions in the data signals and transitions in clock signals. The processing circuitry comprises pass gates that are selectively controlled to delay the latter of the input signals received at substantially the same time. In one embodiment the processing circuitry, or separator circuit, comprises a signal separator circuit that has two controllable current paths. In such an embodiment, whichever signal arrives first in time will delay the transition of the second arriving signal. In another embodiment, the processing circuitry comprises pass transistors that control a propagation path of a first input signal. The pass transistors are controlled by a second input signal. Likewise, whichever signal arrives first in time will delay the transition of the second arriving signal.

Abstract: A highly linear and low voltage mixer is shown. The mixer comprises a first transistor, a second transistor and a third transistor. The first transistor has a gate, source, and drain. The source is connected to the voltage supply and the gate and the drain are connected to an output node. The second transistor has a gate, source, and drain and the drain is connected to the output node, the source is connected to the ground node, and the gate receives a positive phase of the first signal and a positive phase of the second signal. The third transistor has a gate, source, and drain. The drain is connected to the output node, the source is connected to the ground node, and the gate receives a negative phase of the first signal and a negative phase of the second signal. The second and third transistors are turned on and off by the second signal.

Abstract: A method and apparatus for a half-circulator is described. In one embodiment, the half-circulator may be used in a bus between processing units or other logical blocks using small-signaling with current-mode logic. For this reason, the half-circulator implements addition and subtraction of small-signal currents. Using small-signal signaling, the half-circulator (and the bus containing half-circulators by extension) improves robustness against noise from the power supply lines, and minimizes the added jitter suffered by other schemes when implemented on a bus with several tapping nodes.