Abstract: A semiconductor manufacturing process wherein high aspect ratio deep openings are plasma etched in a dielectric layer using an etchant gas which includes a fluorocarbon, a sulfur-containing gas, an oxygen-containing gas and an optional carrier gas. The etchant gas can include CxFyHz such as C4F8, SO2, O2 and Ar. The combination of the sulfur-containing gas and the oxygen-containing gas provides profile control of the deep openings.

Abstract: A plasma processing chamber is provided. The plasma processing chamber includes a bottom electrode configured to support a substrate and a top electrode located over the bottom electrode. The plasma processing chamber further includes a plasma confinement assembly designed to transition between a closed orientation and an open orientation. In the closed orientation, the plasma confinement assembly defines a first volume for plasma during processing, and in the open orientation, the plasma confinement assembly defines a second volume for plasma during processing which is larger than the first volume.

Abstract: A vacuum plasma chamber for processing a workpiece includes first and second electrodes for electrical coupling with gas in the chamber and respectively connected to first and second relatively high and low frequency RF sources. The chamber includes a wall at a reference potential and a plasma confinement region spaced from the wall. A filter arrangement connected to the sources and the electrodes enables current from the first source to flow to the first electrode, prevents the substantial flow of current from the first source to the second electrode and the second source, and enables current from the second source to flow to the first and second electrodes and prevents the substantial flow of current from the second source to the first source.

Abstract: The invention relates to a plasma processing reactor apparatus for semiconductor processing a substrate. The apparatus includes a chamber. The apparatus further includes a top electrode configured to be coupled to a first RF power source having a first RF frequency and a bottom electrode configured to be coupled to second RF power source having a second RF frequency that is lower than the first RF frequency. The apparatus additionally includes an insulating shroud that lines an interior of the chamber, the insulating shroud being configured to be electrically floating during the processing. The apparatus further includes a perforated plasma confinement ring disposed outside of an outer periphery of the bottom electrode, a top surface of the perforated plasma confinement ring being disposed below a top surface of the substrate and electrically grounded during the processing.

Abstract: The invention relates to a plasma processing reactor apparatus for semiconductor processing a substrate. The apparatus includes a chamber. The apparatus further includes a top electrode configured to be coupled to a first RF power source having a first RF frequency and a bottom electrode configured to be coupled to second RF power source having a second RF frequency that is lower than the first RF frequency. The apparatus additionally includes an insulating shroud that lines an interior of the chamber, the insulating shroud being configured to be electrically floating during the processing. The apparatus further includes a perforated plasma confinement ring disposed outside of an outer periphery of the bottom electrode, a top surface of the perforated plasma confinement ring being disposed below a top surface of the substrate and electrically grounded during the processing.

Abstract: The invention relates to a plasma processing reactor apparatus for semiconductor processing a substrate. The apparatus includes a chamber. The apparatus further includes a top electrode configured to be coupled to a first RF power source having a first RF frequency and a bottom electrode configured to be coupled to second RF power source having a second RF frequency that is lower than the first RF frequency. The apparatus additionally includes an insulating shroud that lines an interior of the chamber, the insulating shroud being configured to be electrically floating during the processing. The apparatus further includes a perforated plasma confinement ring disposed outside of an outer periphery of the bottom electrode, a top surface of the perforated plasma confinement ring being disposed below a top surface of the substrate and electrically grounded during the processing.

Abstract: Disclosed is a system for processing a semiconductor wafer through plasma etching operations. The system has a process chamber that includes a support chuck for holding the semiconductor wafer and a pair of RF power sources. In another case, the system can be configured such that the electrode is grounded and the pair of RF frequencies are fed to the support chuck (bottom electrode). The system therefore includes an electrode that is positioned within the system and over the semiconductor wafer. The electrode has a center region, a first surface and a second surface. The first surface is configured to receive processing gases from a source that is external to the system and flow the processing gases into the center region. The second surface has a plurality of gas feed holes that are continuously coupled to a corresponding plurality of electrode openings that have electrode opening diameters that are greater than gas feed hole diameters of the plurality of gas feed holes.

Abstract: Disclosed is a method for improving the selectivity of dielectric layers to photoresist layers and base layers. The method is performed in a plasma processing chamber, and the photoresist layer is coated over the dielectric layer. The method includes introducing an etchant source gas into the plasma processing chamber, which consists essentially of a CxFy gas and an N.sub.2 gas. The method further includes striking a plasma in the plasma processing chamber from the etchant source gas. The method additionally includes etching at least a portion of the dielectric layer with the plasma through to a base layer that underlies the dielectric layer. The method is also well suited for anisotropically etching an oxide layer with very high selectivities to Si, Si.sub.3 N.sub.4, TiN, and metal silicides.

Abstract: Electrode designs for reducing the problem of non-uniform etch in large diameter substrates are presented. The electrode opposite the substrate being etched in a plasma reactor can be tailored as to its shape so as to control the uniformity of the etching across the substrate. This is achieved with a number of generally dome-shaped electrode structures including generally cone-shaped electrodes, generally pyramidally-shaped electrodes and generally hemispherically-shaped electrodes. It is believed that non-uniformity of etching is due, at least in part, to excess ion density at the center of the reactor. The dome-shaped electrodes serve to disperse the high concentration of ions from the center of the reactor out toward the periphery of the substrate and thereby even out the ion density distribution across the substrate being etched. The electrodes are useable in diode plasma reactors, triode plasma reactors and ICP plasma reactors.

Abstract: The present invention is directed to a dual frequency capacitively-coupled plasma apparatus for materials processing. According to a first aspect of the present invention, a dual frequency triode reactor includes a VHF (30-300 MHz) RF power supply capacitively coupled to an upper reactor electrode and an HF (0.1-30 MHz) RF power supply capacitively coupled to a lower reactor electrode to which the wafer is attached. The VHF power supply is used to generate and control formation of a low sheath potential, high density plasma for minimum device damage and rapid etching/deposition while the HF power supply is used to provide a DC bias to the wafer substrate. According to a second aspect of the present invention, a tailored, powered upper electrode, at least a portion of which is generally conical in shape, is employed to provide a uniform etch across the diameter of the wafer.