Patents by Inventor Lun Hsieh

Lun Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8828745
    Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 9, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
  • Patent number: 8796695
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 5, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Publication number: 20140175190
    Abstract: Disclosed is a rotary nebulization device installed to a container that contains a liquid to be nebulized, and the rotary nebulization device includes a main body, an electric connection ring, an nebulization ring and a rotary ring. The main body contains a power supply, the electric connection ring, the nebulization ring and the rotary ring sequentially installed on a side of the main body, and the electric connection ring has a first contact electrically coupled to the power supply, and the nebulization ring has an nebulization module electrically coupled to the first contact, and the rotary ring has a second contact corresponding to the first contact. The corresponding container has an opening portion and a liquid storage slot, and the rotary ring is provided for switching the connection and electric conduction between the liquid storage slot and the nebulization module to improve the convenience of operation.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 26, 2014
    Applicant: MICRO BASE TECHNOLOGY CORPORATION
    Inventors: Tun-Ying FANG, Tai-Shuan LIN, Chia-Lun HSIEH, Shao-Ming YANG, Yu-De SU, Chi-San HUNG
  • Publication number: 20140167078
    Abstract: An exemplary lead frame includes a substrate and a bonding electrode, a first connecting electrode, and a second connecting electrode embedded in the substrate. A top surface of the bonding electrode includes a first bonding surface and a second bonding surface spaced from the first bonding surface. A top surface of the first connecting electrode includes a first connecting surface and a second connecting surface spaced from the first connecting surface. Top surfaces of the bonding electrode, the first connecting electrode and the second connecting electrode are exposed out of the substrate to support and electrically connect with light emitting chips. Light emitting chips can be mounted on the lead frame and electrically connect with each other in parallel or in series; thus, the light emitting chips can be connected with each in a versatile way.
    Type: Application
    Filed: October 22, 2013
    Publication date: June 19, 2014
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: YAU-TZU JANG, YU-LIANG HUANG, WEN-LIANG TSENG, PIN-CHUAN CHEN, LUNG-HSIN CHEN, HSING-FEN LO, CHAO-HSIUNG CHANG, CHE-HSANG HUANG, YU-LUN HSIEH
  • Publication number: 20140166776
    Abstract: Disclosed is a constant quantity control nebulization device including a main body, a nebulization module, a fixing plate and a rotary ring, and the device is installed to a container that contains a liquid to be nebulized. A first liquid storage space with a predetermined volume is defined at the top of the main body, and the nebulization module is installed in the main body and interconnected to the first liquid storage space, and the fixing plate is fixed onto the main body and has a first through hole, the rotary ring is sheathed on the top of the main body and axially coupled to the fixing plate, and the rotary ring has a second through hole corresponding to the first through hole. The consumption of the liquid to be nebulized can be controlled by rotating the rotary ring to improve the convenience of operation significantly.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 19, 2014
    Applicant: MICRO BASE TECHNOLOGY CORPORATION
    Inventors: TUN-YING FANG, TAI-SHUAN LIN, CHIA-LUN HSIEH, SHAO-MING YANG, YU-DE SU, CHI-SHAN HUNG
  • Patent number: 8749611
    Abstract: A video conference system built in an internet protocol (IP) network is provided. The system has: a multimedia capturing unit configured to photograph and output a first video signal; a DECT telephone configured to receive sounds and output a first audio signal; and a video conference terminal apparatus, including: an audio processing unit is an audio codec; a video processing unit is an video codec; and a network processing unit for transmitting a first network packet consisting of first audio/video streams generated by the audio/video processing units to the IP network, wherein the network processing unit receives a second network packet consisting of second audio/video streams from the IP network, wherein the second audio/video streams are decoded by the audio/video processing units, respectively, to generate second audio/video signals, which are displayed on the DECT telephone and a display apparatus, respectively.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Quanta Computer Inc.
    Inventors: Barry Lam, Chia-Yuan Chang, Rong-Quen Chen, Chi-Cheng Chang, Huan-Tang Wu, Chih-Wei Sung, I-Chung Chien, Chih-Yin Lin, Ting-Han Huang, Juin-Yi Huang, Hsin-Lun Hsieh, Chao-Chueh Chang, Kang-Wen Lin, Chia-Yi Wu
  • Patent number: 8709910
    Abstract: A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee, Min-Chung Cheng
  • Publication number: 20140109635
    Abstract: A lock assembly has a body, a latching device, a linking device and a locking mechanism. The linking device is connected to and driven by the latching device. The locking mechanism is moveably mounted in the body and has a bolt base, a pushing element, a lever element and a locking bolt. The bolt base is mounted slidably in the body. The locking bolt is slidably mounted on the bolt base and is driven to retract into or completely extends out from the body with the transmission of the pushing element and the lever element.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Applicant: DOOR & WINDOW HARDWARE CO.
    Inventors: Wei-Hung CHANG, Chih-Lun HSIEH
  • Patent number: 8674433
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Publication number: 20140070870
    Abstract: The present invention discloses a multipurpose half bridge signal output circuit. The multipurpose half bridge signal output circuit is capable of selectively operating under a charge sharing mode or a gate pulsing modulation mode. The multipurpose half bridge signal output circuit includes: a first output pin; a second output pin; a first circuit zone having a first common end coupled to the first output pin; and a second circuit zone having a second common end coupled to the second output pin.
    Type: Application
    Filed: August 23, 2013
    Publication date: March 13, 2014
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Wei-Lun Hsieh, Hung-Sung Chu, Chung-Hsien Tso
  • Patent number: 8665230
    Abstract: A sensing display device including a display panel and a sensing element is provided. The display panel includes at least a plurality of pixel units, and the pixel units are arranged along a primary direction. The sensing element is disposed on the pixel units and includes at least a plurality of sensor units. Each of the sensor units includes a mesh-pattern electrode, and the mesh-pattern electrode includes a plurality of first traces having conductivity. At least one of the first traces is substantially extended along a first direction, wherein a first angle is formed between the first direction and the primary direction, and the first angle is an acute angle.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: March 4, 2014
    Assignee: Au Optronics Corporation
    Inventors: Po-Yuan Liu, Yi-Long Wang, Chun-Ku Kuo, Ming-Lun Hsieh, Hung-Wen Chou
  • Patent number: 8643993
    Abstract: The present invention discloses a short-circuit detection circuit and a short-circuit detection method. The short-circuit detection circuit detects whether an output node is short-circuited to a first predetermined level. A first switch circuit which is controlled by a control signal is coupled between the output node and a second predetermined level. The short-circuit detection circuit includes: a determination circuit, which is coupled between the output node and the second predetermined level, wherein when the determination circuit is enabled, it generates a determination signal according to whether the output node is short-circuited to the first predetermined level; and a second switch circuit, which generates a short-circuit detection signal according to the determination signal.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: February 4, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Kuo-Chen Tsai, Wei-Lun Hsieh, Tung-Han Tsai, Ming-Jun Hsiao
  • Publication number: 20130341638
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Publication number: 20130288448
    Abstract: A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Inventors: Chin-I Liao, Chia-Lin Hsu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee, Min-Chung Cheng
  • Publication number: 20130217271
    Abstract: An electrical connector includes a first terminal and a second terminal. The second terminal is fixed at the first terminal and enclosed by the first terminal, in which the second terminal includes a tube-shaped structure, the tube-shaped structure has a clipping portion and two end-surfaces, the two end-surfaces lean against each other to form a seam. The inner diameter of the clipping portion is smaller than the inner diameters of other portions of the tube-shaped structure. When a third terminal of a coupling connector is inserted into the tube-shaped structure to make the tube-shaped structure elastically deformed, the two end-surfaces are separated from each other and the clipping portion clips the third terminal.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 22, 2013
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Yi-Hsun Lin, Yen-Chih Chen, Wei-Chih Shih, Tzu-Chiang Mi, Ya-Lun Hsieh, Hung-Tien Chang, Feng-Ju Lee
  • Publication number: 20130161672
    Abstract: An LED package includes a substrate, two electrodes, an LED die and a lens. The substrate includes a top surface, a bottom surface, a plurality of side surfaces interconnecting the top surface with the bottom surface, and two opposite notches depressed downward from lateral peripheral portions of the top surface. The two electrodes penetrate through the substrate, and each of the two electrodes is exposed at both the top surface and the bottom surface of the substrate. The LED die is arranged on the substrate and electrically connected to the two electrodes. The lens is arranged on the substrate and covers the LED die. The lens includes a contacting surface adjoining the top surface of the substrate, and two protrusions extending from lateral peripheral portions of the contacting surface and respectively embedded in the two notches.
    Type: Application
    Filed: August 30, 2012
    Publication date: June 27, 2013
    Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventor: YU-LUN HSIEH
  • Patent number: 8451250
    Abstract: The present invention relates to a capacitive touch panel. In one embodiment, the capacitive touch panel includes a plurality of driving electrodes and a plurality of sensing electrodes spatially arranged in a matrix, and a driver electrically coupled to the touch sensor matrix and configured to generate a driving signal to synchronically drive one or more driving electrodes and the sensing electrodes, such that at least one sensing electrode is not driven by the driving signal. The remaining driving electrodes are grounded. The not-driven sensing electrodes sense and transmit a sensing signal of a touch.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: May 28, 2013
    Assignee: Au Optronics Corporation
    Inventors: Ming-Lun Hsieh, Chun-Ku Kuo, Po-Yuan Liu
  • Publication number: 20130128395
    Abstract: The present invention discloses a short-circuit detection circuit and a short-circuit detection method. The short-circuit detection circuit detects whether an output node is short-circuited to a first predetermined level. A first switch circuit which is controlled by a control signal is coupled between the output node and a second predetermined level. The short-circuit detection circuit includes: a determination circuit, which is coupled between the output node and the second predetermined level, wherein when the determination circuit is enabled, it generates a determination signal according to whether the output node is short-circuited to the first predetermined level; and a second switch circuit, which generates a short-circuit detection signal according to the determination signal.
    Type: Application
    Filed: February 10, 2012
    Publication date: May 23, 2013
    Inventors: Kuo-Chen Tsai, Wei-Lun Hsieh, Tung-Han Tsai, Ming-Jun Hsiao
  • Publication number: 20130122698
    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Min-Ying Hsu, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8440511
    Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: May 14, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Min-Ying Hsu, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee