Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

Abstract: A depth estimation from focus method and system includes receiving input image data containing focus information, generating an intermediate attention map by an AI model, normalizing the intermediate attention map into a depth attention map via a normalization function, and deriving expected depth values for the input image data containing focus information from the depth attention map. The AI model for depth estimation can be trained unsupervisedly without ground truth depth maps. The AI model of some embodiments is a shared network estimating a depth map and reconstructing an AiF image from a set of images with different focus positions.

Abstract: The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

Abstract: An automatic robotic arm system and a coordinating method for robotic arm and computer vision thereof are disclosed. A beam-splitting mirror splits an incident light into a visible light and a ranging light and respectively guides to an image capturing device and an optical ranging device arranged in the different reference axes. In a calibration mode, a transformation relation is computed based on a plurality of the calibration postures and corresponding calibration images. In an operation mode, a mechanical space coordinate is determined based on an operation image and the transformation relation, and the robotic arm is controlled to move based on the mechanical space coordinate.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: The disclosure is directed to a method of handling conditional handover with a candidate secondary cell group (SCG), a source master node, and a user equipment, which may be used to solve the above technical problems. The method includes: determining, by the source MN, a first execution condition of a first candidate primary cell (PCell); and receiving, by the source MN from a first candidate MN, a parameter of a second execution condition of a first candidate primary SCG cell (PSCell).

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

Abstract: A projection device including a casing, a light source module, an optical engine module and a projection lens is provided. A front cover, a rear cover, a first side cover, a second side cover, an upper cover and a lower cover of the casing surround an accommodating space. The light source module includes a first and a second light sources, and a first and a second light source heat dissipation modules. The lower cover has a first, a second and a third air inlets. The first and the second side covers respectively have a first and a second air outlets. The first and the second light source heat dissipation modules are correspondingly disposed above the first air inlet and correspond to the first air outlet. The second and the third air inlets are respectively disposed below two sides of the projection lens and adjacent to the front cover.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

Abstract: The present disclosure is directed to methods for the formation of high-voltage nano-sheet transistors and low-voltage gate-all-around transistors on a common substrate. The method includes forming a fin structure with first and second nano-sheet layers on the substrate. The method also includes forming a gate structure having a first dielectric and a first gate electrode on the fin structure and removing portions of the fin structure not covered by the gate structure. The method further includes partially etching exposed surfaces of the first nano-sheet layers to form recessed portions of the first nano-sheet layers in the fin structure and forming a spacer structure on the recessed portions. In addition, the method includes replacing the first gate electrode with a second dielectric and a second gate electrode, and forming an epitaxial structure abutting the fin structure.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A power conversion apparatus supplies power to a load, and the power conversion apparatus includes a power switch, a transformer, and a control module. The control module alternately turns on and turns off a power switch of the power conversion apparatus to convert an input voltage into an output voltage through the transformer. When the power switch is turned off, a primary side of the transformer generates a resonance voltage. The control module sets a predetermined counting threshold according to the output voltage, and sets a blanking time interval according to a feedback signal related to the load. After the blanking time interval ends, the control module counts a number of an oscillation turning point generated by the resonance voltage due to the oscillation of the resonance voltage. When the number reaches the predetermined counting threshold, the control module turns on the power switch.

Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.

Abstract: An optical mechanism is provided, including a housing, a base, and a metal supporting member. The housing has a top cover and a sidewall connected to the top cover, wherein the top cover and the sidewall comprises plastic material. The base is connected to the housing, wherein an optical element is accommodated in a space between the housing and the base. At least a part of the metal supporting member is embedded in the housing.