Abstract: The invention includes a magnetic memory cell. The magnetic memory cell includes a reference layer having a preset magnetization. A barrier layer is formed adjacent to the reference layer. A sense layer is formed adjacent to the barrier layer. A first conductive write line is electrically connected to the reference layer. The magnetic memory cell further includes a second conductive write line having a gap, the gap being filled by at least a portion of the sense layer. A write current conducting through the second conductive write line is at least partially conducted through the portion of the sense layer, the write current increasing a temperature of the sense layer.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.

Abstract: A resistive cross point array memory device comprising a plurality of word lines extending in a row direction, a plurality of bit lines extending in a column direction such that a plurality of cross points is formed at intersections between the word and bit lines, and at least one memory element formed in at least one of the cross points. The memory element comprises a first tunnel junction having a bottom conductor, a top conductor, a barrier layer adjacent the bottom conductor, and wherein the bottom conductor comprises a non-uniform upper surface.

Abstract: A storage device comprising a magnetic storage medium mounted in a first plane, a read and write mechanism mounted in a second plane that is parallel to the first plane and configured to write information to the magnetic storage medium, and a micromover configured to move the magnetic storage medium in a first direction parallel to the first plane and configured to move the magnetic storage medium in a second direction parallel to the first plane and perpendicular to the first direction.

Abstract: A data storage device includes a cross point array of resistive memory elements and a plurality of blocking elements. The device is arranged in groups. Each group includes series-connected memory elements and a blocking element. The blocking elements are used to prevent sneak path currents from interfering with sense currents during read operations.

Abstract: This invention provides a thermal-assisted switching magnetic memory storage device. In a particular embodiment, a cross-point array of conductive rows and columns is provided with offset tunnel junction magnetic memory cells provided proximate to the intersections between the rows and columns. A looping write conductor is provided close to, but not in electrical contact with each memory cell. The looping write conductor loops across the top and bottom of each memory cell. Each magnetic memory cell provides a magnetic data layer characterized by a material wherein the coercivity is decreased upon an increase in temperature, an intermediate layer, and a reference layer. The magnetic fields provided by the looping write conductor during a write operation are not sufficient to alter the magnetic orientation of an unheated data layer, but may alter the data layer of a memory cell warmed by a bias current tunneling through the memory cell.

Abstract: The invention includes a magnetic memory cell. The magnetic memory cell includes a reference layer having a preset magnetization. A barrier layer is formed adjacent to the reference layer. A sense layer is formed adjacent to the barrier layer. A first conductive write line is electrically connected to the reference layer. The magnetic memory cell further includes a second conductive write line having a gap, the gap being filled by at least a portion of the sense layer. A write current conducting through the second conductive write line is at least partially conducted through the portion of the sense layer, the write current increasing a temperature of the sense layer.

Abstract: A memory device including an array of magnetic storage cells is disclosed. Each magnetic storage cell in the array includes a set of conductors used to write data to a storage cell and a second set of conductors used to heat the magnetic storage cell and read data from the magnetic storage cell. The magnetic storage cells can be used in electronic systems such as a computer system or consumer electronic system.

Abstract: A magnetic memory device can include a synthetic ferrimagnetic data, a soft reference layer and a tunneling layer. The synthetic ferrimagnetic data layer has a magnetic moment directable to a first orientation and a second orientation. The soft reference layer has a lower coercivity than the synthetic ferrimagnetic data layer. The tunneling layer has electrical resistance qualities which are influenced by magnetic moment orientations of the synthetic ferrimagnetic data layer and the soft reference layer.

Abstract: The invention includes a stacked magnetic memory structure. The magnetic memory structure includes a stacked magnetic memory structure. The first layer includes a first plurality of magnetic tunnel junctions. A second layer is formed adjacent to the first layer. The second layer includes a second plurality of magnetic tunnel junctions. The stacked magnetic memory structure further includes a common first group conductor connected to each of the first plurality of magnetic tunnel junctions and the second plurality of magnetic tunnel junctions.

Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

Abstract: A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.

Abstract: A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: A memory device includes a data layer having a magnetization that can be oriented in first and second directions; and a synthetic ferrimagnet reference layer. The data and reference layers have different coercivities.

Abstract: A memory cell sensor including an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.