Abstract: A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.

Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.

Abstract: A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: The invention includes a memory cell sensor. The memory cell sensor includes an integrator for sensing a logical state of a memory cell. An integrator calibration circuit provides a corrective bias to the integrator, the corrective bias being based upon a difference between an initial integrator output value and a reference value. Another embodiment of the invention includes a method of sensing a logical state of a memory cell. The memory cell being sensed by an integrator. The method includes determining an initial integrator output value when a corrective bias of the integrator is zeroed, generating a correction value by comparing the initial integrator output value to a reference value, and applying the correction value to the corrective bias of the integrator.

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: An exemplary nonvolatile memory array comprises a substrate and a plurality of memory cells formed on the substrate, each of the memory cells being addressable via at least first and second conductors during operations. An exemplary memory cell in the exemplary memory array includes a ferromagnetic annular data layer having an opening, the opening enabling the second conductor to electrically contact the first conductor, an intermediate layer on at least a portion of the annular data layer, and a soft reference layer on at least a portion of the intermediate layer.

Abstract: The present invention is a magnetic memory device and method. In one embodiment a present invention magnetic memory device includes a synthetic ferrimagnetic data, a soft reference layer and a tunneling layer. The synthetic ferrimagnetic data layer has a magnetic moment directable to a first orientation and a second orientation. The soft reference layer has a lower coercivity than the synthetic ferrimagnetic data layer. The tunneling layer has electrical resistance qualities which are influenced by magnetic moment orientations of the synthetic ferrimagnetic data layer and the soft reference layer.

Abstract: A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.

Abstract: A synthetic ferrimagnet reference layer for a magnetic storage device. The reference layer has first and second layers of magnetic material operable to be magnetized in first and second magnetic orientations. A spacer layer between the layers of magnetic material is of suitable dimensions to magnetically couple the magnetic layers in opposite directions. The layers of magnetic material have substantially the same coercivities.

Abstract: A synthetic ferrimagnet reference layer for a magnetic storage device. The reference layer has first and second layers of magnetic material operable to be magnetized in first and second magnetic orientations. A spacer layer between the layers of magnetic material is of suitable dimensions to magnetically couple the magnetic layers in opposite directions. The layers of magnetic material have substantially the same coercivities.

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.

Abstract: A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.

Abstract: A memory device includes a data layer having a magnetization that can be oriented in first and second directions; and a synthetic ferrimagnet reference layer. The data and reference layers have different coercivities.

Abstract: A device having a magneto-resistive element, a first conductor proximate to the magneto-resistive element, and a second conductor proximate to the magneto-resistive element. The magneto-resistive element is exposed to a magnetic field generated by a first electrical pulse carried by the first conductor. The magneto-resistive element is also exposed to a magnetic field generated by a second electrical pulse carried by the second conductor. The second electrical pulse is delayed relative to the first electrical pulse.

Abstract: A data storage device that includes a novel resistive cross point memory cell array and a method of making the data storage device are described. The resistive cross point memory cell array enables high-density fabrication and high-speed operation with isolation diodes that have practical dimensions and current density characteristics. In addition, the data storage device includes a novel equipotential isolation circuit that substantially avoids parasitic currents that otherwise might interfere with the sensing of the resistance state of the memory cells. In one aspect, the memory cells of the resistive cross point memory cell array are arranged into multiple groups of two or more memory cells. The memory cells of each group are connected between a respective word line and a common isolation diode that is coupled to a bit line.