Patents by Inventor Lurng-Shehng Lee

Lurng-Shehng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11615959
    Abstract: A silicon carbide (carborundum) semiconductor device and a manufacturing method thereof. The manufacturing method of the silicon carbide semiconductor device comprises the following steps of: providing a semiconductor component structure on a silicon carbide substrate, the semiconductor component structure being formed on a front side of the silicon carbide substrate; and forming a multi-layer structure on a back side of the silicon carbide substrate, the multi-layer structure comprising a plurality of ohmic contact layers and a plurality of gettering material layers. By dispersing the gettering material into multiple layers, and by adjusting a thickness combination of the ohmic contact layer and the gettering material layer, even if the gettering material layer is relatively thin (thickness sufficient for balling), a content is still sufficient for gettering carbon and reducing carbon aggregation and accumulation.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 28, 2023
    Assignee: HESTIA POWER SHANGHAI TECHNOLOGY INC.
    Inventors: Lurng-Shehng Lee, Chien-Chung Hung, Chwan-Ying Lee
  • Publication number: 20230064733
    Abstract: A silicon carbide (carborundum) semiconductor device and a manufacturing method thereof. The manufacturing method of the silicon carbide semiconductor device comprises the following steps of: providing a semiconductor component structure on a silicon carbide substrate, the semiconductor component structure being formed on a front side of the silicon carbide substrate; and forming a multi-layer structure on a back side of the silicon carbide substrate, the multi-layer structure comprising a plurality of ohmic contact layers and a plurality of gettering material layers. By dispersing the gettering material into multiple layers, and by adjusting a thickness combination of the ohmic contact layer and the gettering material layer, even if the gettering material layer is relatively thin (thickness sufficient for balling), a content is still sufficient for gettering carbon and reducing carbon aggregation and accumulation.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Lurng-Shehng LEE, Chien-Chung HUNG, Chwan-Ying LEE
  • Publication number: 20220223730
    Abstract: A trench silicon carbide metal-oxide semiconductor field effect transistor includes a silicon carbide semiconductor substrate and a trench metal-oxide semiconductor field effect transistor, the field effect transistor includes a trench vertically arranged and penetrating along a first horizontal direction, a gate insulating layer formed on an inner wall of the trench, a first poly gate formed on the gate insulating layer, a shield region formed outsides and below the trench, and a field plate arranged between a bottom wall of the trench and the shield region, and the field plate has semiconductor doping and is laterally in contact to a current spreading layer to deplete electrons of the current spreading layer when a reverse bias voltage is applied.
    Type: Application
    Filed: January 11, 2021
    Publication date: July 14, 2022
    Inventors: Chien-Chung HUNG, Kuo-Ting CHU, Lurng-Shehng LEE, Chwan-Yin LI
  • Patent number: 10483389
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 19, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 9368650
    Abstract: A SiC junction barrier controlled Schottky rectifier includes a SiC substrate, a n-type drift layer, a p-type doping region, a plurality of junction field-effect regions, a first metal layer and a second metal layer. The drift layer is disposed on the SiC substrate. The junction field-effect regions are disposed in the drift layer and are surrounded by the p-type doping region. The first metal layer is disposed on the drift layer. The second metal layer is disposed at one side of the SiC substrate away from the drift layer. Through N circular regions and (N?1) inter-circle regions each connecting two of the circular regions, as well as geometric characteristics of the circular regions and the inter-circle regions, a leakage current of devices is effectively reduced and ruggedness is increased to improve an issue of a large leakage current of a conventional Schottky barrier diode.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: June 14, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Publication number: 20160111533
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 21, 2016
    Inventors: Cheng-Tyng YEN, Chien-Chung HUNG, Chwan-Ying LEE, Lurng-Shehng LEE
  • Patent number: 9246016
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 26, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Publication number: 20160005883
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Application
    Filed: March 25, 2015
    Publication date: January 7, 2016
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 9018640
    Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 28, 2015
    Assignee: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Lurng-Shehng Lee, Chwan-Ying Lee
  • Publication number: 20150102362
    Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.
    Type: Application
    Filed: March 4, 2014
    Publication date: April 16, 2015
    Applicant: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Lurng-Shehng Lee, Chwan-Ying Lee
  • Patent number: 8956963
    Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: February 17, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tyng Yen, Kuan-Wei Chu, Lurng-Shehng Lee, Chwan-Ying Lee
  • Publication number: 20140145207
    Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.
    Type: Application
    Filed: July 2, 2013
    Publication date: May 29, 2014
    Inventors: Cheng-Tyng YEN, Kuan-Wei CHU, Lurng-Shehng LEE, Chwan-Ying LEE
  • Patent number: 7851843
    Abstract: A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 14, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Yuan Lee, Chieh-Shuo Liang, Lurng-Shehng Lee
  • Patent number: 7781298
    Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 24, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Hengyuan Lee, Lurng-Shehng Lee, Ching Chiun Wang, Pei-Jer Tzeng
  • Patent number: 7700988
    Abstract: A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: April 20, 2010
    Assignee: Industrail Technology Research Institute
    Inventors: Cha-Hsin Lin, Ching-Chiun Wang, Lurng-Shehng Lee
  • Patent number: 7683374
    Abstract: A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: March 23, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Lurng-Shehng Lee, Ching-Chiun Wang
  • Patent number: 7663177
    Abstract: A non-volatile memory device and fabricating method thereof are provided. In the deposition to form a tunneling dielectric layer, a composite charge trapping layer and a block dielectric layer, an ingredient of a depositing material or the depositing material is adjusted to form a grading energy level structure, such that carriers are trapped or erased more easily in accordance with a variation in grading energy level. Therefore, the carriers are stored more effectively and the probability that the electric leakage occurs is reduced substantially.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: February 16, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Lurng-Shehng Lee, Pei-Jer Tzeng
  • Patent number: 7589373
    Abstract: The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: September 15, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Lurng-Shehng Lee
  • Publication number: 20090114975
    Abstract: The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device.
    Type: Application
    Filed: January 13, 2009
    Publication date: May 7, 2009
    Applicant: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Lurng-Shehng Lee
  • Patent number: 7498631
    Abstract: A sensing memory device disposed on a substrate is provided, which includes a first conductive layer, a second conductive layer and a charge trapping layer. The second conductive layer covers the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: March 3, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Lurng-Shehng Lee