Abstract: A non-volatile memory device and fabricating method thereof are provided. In the deposition to form a tunneling dielectric layer, a composite charge trapping layer and a block dielectric layer, an ingredient of a depositing material or the depositing material is adjusted to form a grading energy level structure, such that carriers are trapped or erased more easily in accordance with a variation in grading energy level. Therefore, the carriers are stored more effectively and the probability that the electric leakage occurs is reduced substantially.

Abstract: A process of forming a high-k gate dielectric layer is applied in forming semiconductor devices such as metal oxide semiconductor transistor or memory devices. A metal layer such as Hf or Zr is formed on a substrate. The substrate is then dipped in an acidic solution such as a nitric acid aqueous solution to form a high-K metal oxide layer including oxides or silicate with a predetermined thickness. Thereby, leakage current is effectively reduced to meet the requirement of currently technology nodes.

Abstract: A process of forming a high-k gate dielectric layer is applied in forming semiconductor devices such as metal oxide semiconductor transistor or memory devices. A metal layer such as Hf or Zr is formed on a substrate. The substrate is then dipped in an acidic solution such as a nitric acid aqueous solution to form a high-K metal oxide layer including oxides or silicate with a predetermined thickness. Thereby, leakage current is effectively reduced to meet the requirement of currently technology nodes.

Abstract: Within an epitaxial base bipolar transistor device and a method for fabricating the epitaxial base bipolar transistor device there is provided: (1) a monocrystalline semiconductor substrate which serves as a collector, in turn having formed thereupon; (2) an epitaxial base layer. Within the epitaxial base bipolar transistor device and method, there is further employed: (1) a pair of inward facing spacers formed over the epitaxial base layer and defining, at least in part, an aperture having at its bottom a portion of the epitaxial base layer; and (2) a pair of outward facing spacers formed over the epitaxial base layer and laminated to a pair of sides of the pair of inward facing spacers opposite the aperture; such that (3) an emitter layer may be formed into the aperture and contacting the epitaxial base layer. The foregoing two pair of spacer layers provide for efficient fabrication of the epitaxial base bipolar transistor device, with enhanced process latitude.

Abstract: With the growing practice of doping gates for MOSFETs with boron, problems have been encountered due to later diffusion of the boron into the active region. To block this, argon ions are implanted into the gate pedestal material prior to doping it with boron. The damage caused by the argon ions results in traps that getter the boron atoms, behaving in effect as a diffusion barrier. The invention is directed specifically to gate pedestals that are less than about 3000 Angstroms thick. Under these conditions it has been determined that the implantation energies of the argon ions should not exceed 80 keV. It is also important that the dosage of argon be in the range from 1.times.10.sup.15 to 1.times.10.sup.16 per cm.sup.2. Preferably doses in excess of 5.times.10.sup.15 should be used as they also lead to improvements in subthreshold swing and hot carrier immunity.