Patents by Inventor Maciej Wojnowski

Maciej Wojnowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930541
    Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 23, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Francesca Arcioni, Maciej Wojnowski
  • Patent number: 10916484
    Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Robert Fehler, Francesca Arcioni, Christian Geissler, Walter Hartner, Gerhard Haubner, Thorsten Meyer, Martin Richard Niessner, Maciej Wojnowski
  • Publication number: 20210036610
    Abstract: A method of manufacturing a power semiconductor system includes providing a power module having one or more power transistor dies and attaching an inductor module to the power module such that the inductor module is electrically connected to a node of the power module. The inductor module includes a substrate with a magnetic material and windings at one or more sides of the substrate. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10833583
    Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20200321295
    Abstract: A semiconductor device comprises a semiconductor chip having a radio-frequency circuit and a radio-frequency terminal, an external radio-frequency terminal, and a non-galvanic connection arranged between the radio-frequency terminal of the semiconductor chip and the external radio-frequency terminal, wherein the non-galvanic connection is designed to transmit a radio-frequency signal.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 8, 2020
    Inventors: Walter HARTNER, Francesca ARCIONI, Birgit HEBLER, Martin Richard NIESSNER, Claus WAECHTER, Maciej WOJNOWSKI
  • Publication number: 20200303815
    Abstract: A packaged radar includes laminate layers, a ground plane associated with at least one of the laminate layers, a transmit antenna and a receive antenna associated with at least one of the laminate layers, and an electromagnetic band gap structure between the transmit antenna and the receive antenna for isolating the transmit antenna and the receive antenna, the electromagnetic band gap structure including elementary cells forming adjacent columns each coupled to the ground plane, and each elementary cell including a conductive planar element and a columnar element coupled to the conductive planar element.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Ashutosh Baheti, Marwa Abdel-Aziz, Mustafa Dogan, Muhammad Tayyab Qureshi, Saverio Trotta, Maciej Wojnowski
  • Publication number: 20200251430
    Abstract: A semiconductor device comprises a substrate having a first surface and a second surface opposite the first surface, at least one connection element arranged on the first surface of the substrate to electrically and mechanically connect the substrate to a printed circuit board, and a radar semiconductor chip arranged on the first surface of the substrate.
    Type: Application
    Filed: January 21, 2020
    Publication date: August 6, 2020
    Inventors: Ernst SELER, Markus Josef LANG, Maciej WOJNOWSKI
  • Publication number: 20200212798
    Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10692824
    Abstract: A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Patent number: 10601314
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20200021002
    Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Maciej Wojnowski, Dirk Hammerschmidt, Walter Hartner, Johannes Lodermeyer, Chiara Mariotti, Thorsten Meyer
  • Publication number: 20200006174
    Abstract: A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 2, 2020
    Inventors: Christian GEISSLER, Walter Hartner, Claus Waechter, Maciej Wojnowski
  • Publication number: 20190221465
    Abstract: A method of forming a chip arrangement is provided. The method includes: arranging a plurality of stacks on a carrier, each stack including a thinned semiconductor chip, a further layer, and a polymer layer between the further layer and the chip, each stack being arranged with the chip facing the carrier; joining the plurality of stacks with each other with an encapsulation material to form the chip arrangement; exposing the further layer; and forming a redistribution layer contacting the chips of the chip arrangement.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 18, 2019
    Inventors: Thomas Kilger, Francesca Arcioni, Maciej Wojnowski
  • Publication number: 20190221531
    Abstract: A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Thorsten Meyer, Walter Hartner, Maciej Wojnowski
  • Publication number: 20190081562
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20190067223
    Abstract: A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Patent number: 10217695
    Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Klaus Pressel, Maciej Wojnowski
  • Patent number: 10186481
    Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Frank Daeche, Zeeshan Umar
  • Publication number: 20180374769
    Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 27, 2018
    Applicant: Infineon Technologies AG
    Inventors: Robert Fehler, Francesca Arcioni, Christian Geissler, Walter Hartner, Gerhard Haubner, Thorsten Meyer, Martin Richard Niessner, Maciej Wojnowski
  • Patent number: 10121751
    Abstract: A semiconductor module comprises an integrated circuit device, the IC device embedded in a compound material, wherein the compound material at least partially extends lateral to the IC device. The semiconductor module further comprises interconnect structures arranged lateral to the IC device to provide at least one external electrical contact; a patch antenna structure integrated in the semiconductor module and electrically connected to the IC device and a layer interfacing the IC device and the compound, wherein the layer comprises first and second planar metal structures coupled to the IC device, wherein the first planar metal structure is electrically connected to the IC device and the interconnect structures and wherein the second planar metal structure is electrically connected to the IC device and the patch antenna structure.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski