Patents by Inventor Magnus Andersson

Magnus Andersson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260091682
    Abstract: An energy storage system of a vehicle equipped with a regenerative braking system and comprising: a battery pack configured to power an electric traction machine and being operable according to predefined limited state of charge (SOC) limits extending from a lower limited SOC limit to an upper limited SOC limit, and predefined extended SOC limits; heat storage tank comprising heating fluid and an electrical heater; a processing circuitry configured to: in response of determining an anticipated cold start operating mode, charge the battery pack in accordance with the extended SOC limits to at least above a level corresponding to that of the upper limited SOC limit, and during subsequent operation of the vehicle and in response of that the SOC of the battery pack is above the upper limited SOC limit, power the electric heater by the regenerative braking system to heat the heating fluid of the heat storage tank.
    Type: Application
    Filed: September 23, 2025
    Publication date: April 2, 2026
    Inventors: Alexander Selander, Magnus Andersson, Roland Kvist
  • Publication number: 20260030832
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.
    Type: Application
    Filed: August 8, 2025
    Publication date: January 29, 2026
    Inventors: Gregory A. MUTHLER, John BURGESS, Henry Packard MORETON, Yury URALSKY, Levi OLIVER, Magnus ANDERSSON, Johannes DELIGIANNIS
  • Patent number: 12475631
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: November 18, 2025
    Assignee: NVIDIA Corporation
    Inventors: Gregory Muthler, John Burgess, Henry Packard Moreton, Yury Uralsky, Levi Oliver, Magnus Andersson, Johannes Deligiannis
  • Publication number: 20250263083
    Abstract: A computer-implemented method is disclosed for detecting potential rollover situations for a vehicle. The method comprises acquiring lateral and vertical wheel forces for the vehicle, and detecting potential rollover based on the lateral and vertical wheel forces as compared between first and second lateral sides of the vehicle. Potential rollover may be detected responsive to the lateral wheel forces being larger for the first lateral side of the vehicle than for the second lateral side of the vehicle, and correspondingly for the vertical wheel forces. Potential rollover may be detected responsive to a sum of the lateral and vertical wheel forces for the first lateral side of the vehicle exceeding a threshold value.
    Type: Application
    Filed: January 17, 2025
    Publication date: August 21, 2025
    Applicant: Volvo Construction Equipment AB
    Inventors: Adithya ARIKERE, Roland KVIST, Magnus ANDERSSON
  • Publication number: 20250182380
    Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
    Type: Application
    Filed: February 3, 2025
    Publication date: June 5, 2025
    Inventors: John BURGESS, Gregory MUTHLER, Nikhil DIXIT, Henry MORETON, Yury URALSKY, Magnus ANDERSSON, Marco SALVI, Christoph KUBISCH
  • Publication number: 20250104333
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • Patent number: 12260486
    Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: March 25, 2025
    Assignee: NVIDIA Corporation
    Inventors: John Burgess, Gregory Muthler, Nikhil Dixit, Henry Moreton, Yury Uralsky, Magnus Andersson, Marco Salvi, Christoph Kubisch
  • Patent number: 12249022
    Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: March 11, 2025
    Assignee: NVIDIA Corporation
    Inventors: John Burgess, Gregory Muthler, Nikhil Dixit, Henry Moreton, Yury Uralsky, Magnus Andersson, Marco Salvi, Christoph Kubisch
  • Publication number: 20250046003
    Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Timo VIITANEN, Levi OLIVER
  • Patent number: 12198251
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: January 14, 2025
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
  • Patent number: 12198252
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: January 14, 2025
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
  • Patent number: 12154214
    Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: November 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Timo Viitanen, Levi Oliver
  • Patent number: 12106423
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: October 1, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
  • Publication number: 20240246035
    Abstract: A filtration system comprising a membrane arrangement comprising membrane housings extending in a first direction and having openings that are located in a common plane and face a common area, and membranes arranged inside the membrane housings and configured to be replaced via the openings, and a lifting arrangement comprising a support frame having a beam that extends along the common plane and is provided vertically above the common area, and a gripper unit slidably attached to the beam and arranged to grip the membranes and transport the membranes in a direction along the common plane.
    Type: Application
    Filed: June 2, 2022
    Publication date: July 25, 2024
    Applicant: Tetra Laval Holdings & Finance S.A.
    Inventor: Magnus ANDERSSON
  • Publication number: 20240095993
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • Publication number: 20240095995
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: NVIDIA Corporation
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • Publication number: 20240095994
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • Publication number: 20240087211
    Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Greg MUTHLER, John BURGESS, Magnus ANDERSSON, Timo VIITANEN, Levi OLIVER
  • Patent number: D997964
    Type: Grant
    Filed: February 26, 2022
    Date of Patent: September 5, 2023
    Assignee: VOLVO CONSTRUCTION EQUIPMENT AB
    Inventors: Mikael Lundaby, Azad Saleh, Magnus Andersson
  • Patent number: D998632
    Type: Grant
    Filed: February 26, 2022
    Date of Patent: September 12, 2023
    Assignee: VOLVO CONSTRUCTION EQUIPMENT AB
    Inventors: Mikael Lundaby, Azad Saleh, Magnus Andersson