Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. The structure includes a first contact connected in a cross couple circuit to at least two gate structures, and a second contact connected to the first contact at a location which is devoid of any via connection.

Abstract: The present disclosure relates to a memory sense amplifier and, more particularly, to a non-volatile memory sense amplifier and methods of use. The structure includes: a first stage amplifier comprising a plurality of non-volatile memory cells connecting to a bit line; a second stage amplifier connecting to the first stage amplifier and a common reference node; and a reference unity gain amplifier connecting to the second stage amplifier through the common reference node and receiving a voltage bias from the first stage amplifier, wherein the reference unity gain amplifier is connected to provide a reference voltage to the second stage amplifier.

Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.

Abstract: A device and method for generating a common bias for a device component having a first circuit powered by a first power supply and a second circuit powered by a second power supply. A method includes: arranging a circuit path in a ring oscillator to replicate a logic depth of both the first circuit and the second circuit, wherein the ring oscillator is controlled by the common bias and a first portion of the circuit path is powered by the first power supply and a second portion of the circuit path is powered by the second power supply; outputting an oscillating signal from the ring oscillator; computing common bias voltages based on the oscillating signal; and applying the common bias voltages to the device component.

Abstract: A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.

Abstract: Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P-silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.

Abstract: A multi-row standard cell and an integrated circuit (IC) structure using the standard cell are provided. The IC structure includes a plurality of cell rows extending in a first direction. At least two cell rows of the plurality of cell rows have different row heights. The IC structure includes a multi-row standard cell positioned in two or more cell rows having different row heights. At least one active region is shared by portions of the multi-row cell across the at least two cell rows. The IC structure may also include one or more asymmetric shared power rails disposed in an asymmetric manner across a row boundary between the at least two cell rows of different row heights. The multi-row standard cells and IC structures allow placement of multi-row cells for mixed track height arrangements in a manner not limited to multiples of row heights.

Abstract: A device and method for generating a common bias for a device component having a first circuit powered by a first power supply and a second circuit powered by a second power supply. A method includes: arranging a circuit path in a ring oscillator to replicate a logic depth of both the first circuit and the second circuit, wherein the ring oscillator is controlled by the common bias and a first portion of the circuit path is powered by the first power supply and a second portion of the circuit path is powered by the second power supply; outputting an oscillating signal from the ring oscillator; computing common bias voltages based on the oscillating signal; and applying the common bias voltages to the device component.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to antenna structures and methods of manufacture. The structure includes an antenna cell comprising a single P-well isolated by a deep trench isolation structure and including at least one diffusion region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to local interconnect power rails merged with upper power rails and methods of manufacture. The structure includes: an active cell including contacts enclosed in active regions; at least one local interconnect power rail connecting to the contacts of the active regions; and at least one power rail above and connected to the at least one local interconnect power rail.

Abstract: Disclosed are embodiments of an integrated circuit (IC) including a first IC section operating in a first voltage domain, a second IC section operating in a second voltage domain, and an isolation structure between the two sections. The isolation structure can include a trench isolation region within a semiconductor layer, isolating first PFETs and, optionally, isolating second PFETs. The isolating first PFETs can be series-connected and can include a first portion of the semiconductor layer between a functional PFET of the first IC section and a first edge of the trench isolation region. Additionally, the isolating first PFETs can operate in the first voltage domain and can be biased so as to remain always off. The isolating second PFETs can be similarly configured between a functional PFET of the second IC section and a second edge of the trench isolation region opposite the first edge.

Abstract: Disclosed design methods and systems employ linear distance marker(s) (LDM(s)) placed over a layout (e.g., of a device or cell) to be analyzed. Nodes are inserted into LDM(s) at intersections with edges of layout shapes. Node-to-node distances (d) for node-to-node segments on LDM(s) are calculated. Design rules with distance specifications (D) are identified and assigned to the segments. A first table is generated and includes, for each segment, the design rule, d, and D. A second table is generated and includes, for each segment in a user-specified subset of segments, the design rule and either D or a user-specified compacted distance specification (C). An output table is generated and includes, for each segment in the subset, the design rule, d, and either D or C. The output table can be analyzed manually and/or automatically to determine if compaction is feasible. Additional embodiments use LDMs to profile devices within a layout.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

Abstract: A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

Abstract: A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor.