Abstract: Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators.

Abstract: Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell.

Abstract: Some embodiments provide techniques and systems for improving the efficiency of area recovery in an electronic design automation (EDA) flow. During operation, the system determines a utilization of a region from a set of regions in a design floorplan. Next, the system performs area recovery (e.g., by using a processor) on the region based at least on the utilization. Specifically, the system can overlay the design floorplan with a grid, wherein the grid comprises a set of grid cells and uses the grid cells as the set of regions. The grid can be associated with a predetermined number of rows and a predetermined number of columns. The system can determine the utilization of the region by calculating the utilization as a cell area of the region divided by a placement area of the region. The utilization can be incrementally calculated during the creation and optimization of the design.

Abstract: Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation.

Abstract: A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.

Abstract: Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

Abstract: A process for synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a cell separation process assigns (x,y) locations to each of the cells based on the weights. The wires are then examined to determine their respective performance characteristics. The wires are iteratively re-weighted, and the cells moved according to the new weightings. Next, the cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of each of the gates can be either scaled up or down accordingly. Again, the nets are iteratively examined and their weights are adjusted appropriately. The cells are spaced apart according to the new weights.

Abstract: A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

Abstract: A method of identifying untestable faults in a logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be untestable if the selected circuit lead were unable to assume a logic 0 and which faults would be untestable if the selected circuit lead were unable to assume a logic 1. Faults that would be untestable in both (hypothetical) cases are identified as untestable faults. Faults which would be untestable if the selected lead were unable to assume a given value may be determined based on an implication procedure. The implication procedure comprises the forward propagation of uncontrollability indicators and the backward propagation of unobservability indicators. An uncontrollability indicator for the given value is assigned to the selected circuit lead and propagated forward through the circuit according to a set of well-defined propagation rules.

Abstract: A method of identifying redundant and untestable faults in a sequential logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be hypothetically undetectable at a given time frame if the selected circuit lead were unable to assume a logic 0 at a starting time frame, and which faults would be hypothetically undetectable at the given time frame if the selected circuit lead were unable to assume a logic 1 at the starting time frame. Faults that would be undetectable at the given time frame in both hypothetical cases are identified as redundant and untestable faults. This analysis may be repeated for each of a plurality of time frames in a range of time frames which includes the starting time frame.