Abstract: A computer-implemented includes performing retiming using a circuit design to determine variation to the circuit design. The circuit design includes a first set of registers with defined power-up states and the variations each comprise a second set of registers that correspond to the first set of registers. The method includes computing and maintaining programmable power-up states for the second set of registers in the variations. The programmable power-up states computed for the second set of registers are equivalent to the defined power-up states of the first set of registers. The method includes identifying registers of the second set of registers involved in an initial state conflict, and performing a mitigating action to resolve the initial state conflict to enable retiming to continue while maintaining functionally equivalent behavior as the circuit design. Various choices of initial states are also explored during retiming to maximize the effect of retiming.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an optimal design on the integrated circuit. Implementing the optimal design may include placing hardware resources within the integrated circuit to decrease or remove overlaps between corresponding hardware resources. A given hardware resource may be defined as a rectangular region, an adjacent hardware resource may be defined as another rectangular region, and together, they may be defined as a hardware resource pair. The hardware resource pair may define an overlap region, with which a cost function may be associated. The cost function may be minimized in conjunction with other types of cost functions using a solver. The solver may generate coordinates that minimize or remove overlap to be implemented in the optimal design.

Abstract: Circuitry for the simulation of partial reconfiguration of a logic design for an integrated circuit device using a hybrid model is provided. The circuitry may create a hybrid model by combining structural model netlists of one or more partial reconfiguration partitions of the logic design with a behavioral model of a static partition of the logic design. The hybrid model may undergo partial reconfiguration verification to ensure that undefined signals do not bypass a freeze bridge and pass from registers in the partial reconfiguration partitions to the static partition, and to ensure that these registers are each in a defined state after the partial reconfiguration operation and a register reset operation are completed.

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.

Abstract: A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process.

Abstract: An integrated circuit design may include registers and combinational logic. The registers may be reset using an original reset sequence. Integrated circuit design computing equipment may perform register moves within the circuit design, whereby registers are moved across one or more portions of the combinational logic. When moving the registers, counter values may be maintained for a group of non-justifiable elements within the combinational logic, across which the registers may move. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that may be used to generate an adjustment sequence. The adjustment sequence may be prepended to the original reset sequence to generate an adjusted reset sequence that properly resets registers within the integrated circuit after registers moves.

Abstract: A method for designing a system on a target device includes identifying a candidate cluster for a node in the system based on a gain value that quantifies utility for the candidate cluster. The candidate cluster is designated as a final cluster for the node when the candidate cluster has a highest gain value among other candidate clusters for each node in the candidate cluster.

Abstract: An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.

Abstract: An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform retiming for the circuit design, where registers are moved across one or more portions of the combinational logic. The registers may be retimed while considering hybrid initial states of the registers. At least some of the registers may have don't-care initial states. When performing backward retiming, initial states of the retimed registers may be computed that is consistent with the original initial state and functionality of the combinational logic while maximizing the number of don't-care initial states. When performing forward retiming across non-justifiable combinational elements, any don't-care initial states may be assumed to be equal to a deterministic binary value, and the initial states of the retimed registers may be computed that is consistent with the original initial states and functionality of the combinational logic.

Abstract: An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via multiple logic signals. The JTAG system includes a JTAG interface receives the multiple logic signals. The JTAG system also includes a JTAG hub instantiated in the first partition and being communicatively coupled to the JTAG interface. The JTAG system further includes JTAG-based logic instantiated in the second partition. The integrated circuit device further includes an interface instantiated in the first partition configured to communicatively couple the JTAG hub to the JTAG-based logic.

Abstract: A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the c-cycle initialization process and indicate to the user logic when c-cycle initialization has completed. The user logic may subsequently begin a user-specified reset sequence. When the user-specified reset sequence ends, the user logic implemented on the integrated circuit may begin normal operations. Additionally, a user reset request may also trigger the auto initialization module to begin a reset process.

Abstract: Circuit design computing equipment may perform register moves within a circuit design. When moving the registers, counter values may be maintained for non-justifiable elements. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that is used to generate a sequence for resetting the modified circuit design after the register moves. The adjustment value may be bound by a user-specified maximum value. This retiming operation may also be verified by performing rewind verification. The rewind verification involves retiming the retimed circuit back to the original circuit, while respecting the counter values. If verification succeeds, the circuit design may be reset using a smaller adjustment value. If verification fails, a correct counter value may be suggested for each clock domain.

Abstract: Configuration data for an integrated circuit may be generated using logic design equipment to implement an circuit design on the integrated circuit. Implementing the circuit design may include placing functional blocks at optimal locations that increase the maximum operating frequency of the integrated circuit implementing the optimal circuit design. Logic design equipment may perform timing analysis on an initially placed circuit design that includes initially placed functional blocks. The timing analysis may identify one or more critical paths that may be shortened by moving the critical functional blocks within the circuit design to candidate placement locations. A levelized graph representing possible candidate locations and paths between the possible candidate locations may be traversed in a breadth-first search to generate a shortest updated critical path. The critical functional blocks may be moved to candidate locations corresponding to the updated critical path.

Abstract: A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Whether the retimed design is structurally correct is verified by performing register retiming on the retimed design.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the retiming of registers in the system driven by a different clock.