Abstract: A method for performing rewind functional verification includes identifying state variables that model the number of registers on each edge of a retiming graph for an original design and a retimed design. Random variables are identified that model retiming labels representing a number and direction of register movement relative to a node on a retiming graph for the retimed design. A retiming constraint is identified for each edge on the retiming graph for the design, wherein the retiming constraint reflects a relationship between the state variables and the random variables. A random variable that models a retiming label at a source of an edge is recursively substituted for a random variable that models a retiming label at a sink of the edge when a number of registers on the edge is unchanged after register retiming.

Abstract: A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. Register retiming is performed on the retimed design. The retimed design is determined to be structurally correct in response to determining that the performing register retiming on the retimed design results in the original design.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver.

Abstract: A collocated device functioning as a configurator can use short and long button activations to enter a configuration state, open a timing window, and force client devices currently joined to a network to rejoin the network. If the collocated device functioning as a configurator is unconfigured, a short (or long) button activation can initiate a configuration sequence. A short button activation on that same collocated device, once configured, can cause the device to open a configurator timing window, during which one or more devices can be provided the information necessary to securely communicate on a network. A long (or short) button activation can be used to force all currently connected client devices, or rejoin the network using a new Service Set Identifier (SSID) or passphrase.

Abstract: Systems and techniques are described for solving an optimization problem using a constraints solver. A set of constraints that correspond to the optimization problem can be generated. Next, a set of upper bound constraints can be added to the set of constraints, wherein the set of upper bound constraints imposes an upper bound on one or more variables that are used in an objective function of the optimization problem. Next, the embodiments can iteratively perform the following set of operations on a computer: (a) solve the set of constraints using the constraints solver; (b) responsive to the constraints solver returning a solution, decrease the upper bound; and (c) responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increase the upper bound. The solution with the lowest upper bound value can be outputted as the optimal solution for the optimization problem.

Abstract: A constraints problem can be created based on a gate-sizing optimization problem for a portion of a circuit design. The constraints problem can comprise a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem. The constraints problem can be repeatedly solved using a constraints solver to obtain a solution of the gate-sizing optimization problem. Specifically, prior to each invocation of the constraints solver, the upper bound can be increased or decreased based at least on a result returned by a previous invocation of the constraints solver.

Abstract: Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.

Abstract: Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order.

Abstract: Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order.

Abstract: Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order.

Abstract: Aspects of a method and system for improved communication network setup utilizing extended terminals are presented. Aspects of the method may comprise configuring a wireless Ethernet terminal functioning as a client station by a configurator via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces. Aspects of the system may comprise a collocated device functioning as a configurator that configures a wireless Ethernet terminal functioning as a client station via a network. The configured wireless Ethernet terminal may wirelessly receives information from a wireless station, and communicate the wirelessly received information to at least one of a plurality of wired stations via at least one of a plurality of corresponding wired interfaces.

Abstract: Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results.

Abstract: A collocated device functioning as a configurator can use short and long button activations to enter a configuration state, open a timing window, and force client devices currently joined to a network to rejoin the network. If the collocated device functioning as a configurator is unconfigured, a short (or long) button activation can initiate a configuration sequence. A short button activation on that same collocated device, once configured, can cause the device to open a configurator timing window, during which one or more devices can be provided the information necessary to securely communicate on a network. A long (or short) button activation can be used to force all currently connected client devices, or rejoin the network using a new Service Set Identifier (SSID) or passphrase.

Abstract: Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design.

Abstract: Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches.

Abstract: Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.

Abstract: Certain aspects of a method for enabling exchange of information in a secure communication system may comprise configuring at least one 802.11 client station via authentication enablement information comprising data that specifies a time period during which configuration is allowed. The data that specifies a time period during which configuration is allowed may comprise a configuration window open field, which indicates a period when a configuration setup window is open. At least one client station may be configured via the authentication enablement information comprising recently configured data, which indicates whether at least one configurator has configured at least one other client station within the time period during which the configuration is allowed.

Abstract: Systems and techniques are described for solving an optimization problem using a constraints solver. A set of constraints that correspond to the optimization problem can be generated. Next, a set of upper bound constraints can be added to the set of constraints, wherein the set of upper bound constraints imposes an upper bound on one or more variables that are used in an objective function of the optimization problem. Next, the embodiments can iteratively perform the following set of operations on a computer: (a) solve the set of constraints using the constraints solver; (b) responsive to the constraints solver returning a solution, decrease the upper bound; and (c) responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increase the upper bound. The solution with the lowest upper bound value can be outputted as the optimal solution for the optimization problem.

Abstract: Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized.

Abstract: Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization.