Patents by Inventor Makoto Furuno

Makoto Furuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110197815
    Abstract: An object is to provide a film deposition apparatus in which the amount of leakage from the outside of the chamber to the inside of the chamber is reduced. Even if leakage occurs from the outside of the chamber to the inside of the chamber, oxygen and nitrogen included in an atmosphere that surrounds the outer wall of the chamber are reduced as much as possible and the atmosphere is filled with a noble gas or hydrogen, whereby the inside of the chamber is kept cleaner at 1/100 or less, preferably, 1/1000 or less of oxygen concentration and nitrogen concentration than those in the air. Since the space with high airtightness is provided adjacent to the outside of the chamber, the chamber is covered with a bag and a high-purity argon gas is supplied to the bag.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Publication number: 20110193087
    Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 11, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Satoshi TORIUMI, Tomokazu YOKOI, Makoto FURUNO
  • Publication number: 20110186850
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Application
    Filed: April 13, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Shinji MAEKAWA, Makoto FURUNO, Osamu NAKAMURA, Keitaro IMAI
  • Patent number: 7989273
    Abstract: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: August 2, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuhiro Ichijo, Makoto Furuno, Takashi Ohtsuki, Kenichi Okazaki, Tetsuhiro Tanaka, Seiji Yasumoto
  • Patent number: 7947544
    Abstract: An object is to provide a film deposition apparatus in which the amount of leakage from the outside of the chamber to the inside of the chamber is reduced. Even if leakage occurs from the outside of the chamber to the inside of the chamber, oxygen and nitrogen included in an atmosphere that surrounds the outer wall of the chamber are reduced as much as possible and the atmosphere is filled with a noble gas or hydrogen, whereby the inside of the chamber is kept cleaner at 1/100 or less, preferably, 1/1000 or less of oxygen concentration and nitrogen concentration than those in the air. Since the space with high airtightness is provided adjacent to the outside of the chamber, the chamber is covered with a bag and a high-purity argon gas is supplied to the bag.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 24, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Publication number: 20110059562
    Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Sachiaki TEDUKA, Satoshi TORIUMI, Makoto FURUNO, Yasuhiro JINBO, Koji DAIRIKI, Hideaki KUWABARA
  • Patent number: 7888167
    Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: February 15, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Toriumi, Tomokazu Yokoi, Makoto Furuno
  • Patent number: 7842992
    Abstract: It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: November 30, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Patent number: 7833845
    Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
  • Patent number: 7786526
    Abstract: It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 31, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tamae Takano, Makoto Furuno, Yoshinobu Asami, Shunpei Yamazaki
  • Patent number: 7709843
    Abstract: According to the present invention, which is a display device in which a light-emitting element where an organic substance generating luminescence referred to as electroluminescence or a medium including a mixture of an organic substance and an inorganic substance is sandwiched between electrodes is connected to a TFT, the invention is to manufacture a display panel by forming at least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask layer for forming a predetermined pattern is formed by a method capable of selectively forming a pattern. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object and by forming a conductive layer or an insulating layer is used as a method capable of selectively forming a pattern.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Patent number: 7692232
    Abstract: A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: April 6, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20100047998
    Abstract: A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate.
    Type: Application
    Filed: October 29, 2009
    Publication date: February 25, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 7638408
    Abstract: A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 7611930
    Abstract: In a case of forming a bottom-gate thin film transistor, a step of forming a microcrystalline semiconductor film over a gate insulating film by a plasma CVD method, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film are performed. In the step of forming the microcrystalline semiconductor film, the pressure in the reaction chamber is set at or below 10?5 Pa once, the substrate temperature is set in the range of 120° C. to 220° C., plasma is generated by introducing hydrogen and a silicon gas, hydrogen plasma is made to act on a reaction product formed on a surface of the gate insulating film to perform removal while performing film formation. Moreover, the plasma is generated by applying a first high-frequency electric power of an HF band a second high-frequency electric power of a VHF band superimposed on each other.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: November 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Makoto Furuno, Satoshi Toriumi, Yasuhiro Jinbo, Koji Dairiki
  • Publication number: 20090267066
    Abstract: To provide a photoelectric conversion device with improved photoelectric conversion characteristics and cost competitiveness. A photoelectric conversion device including a semiconductor junction has a semiconductor layer in which a needle-like crystal is made to grow over an impurity semiconductor layer. The impurity semiconductor layer is formed of a microcrystalline semiconductor and includes an impurity imparting one conductivity type. An amorphous semiconductor layer is deposited on a microcrystalline semiconductor layer by setting the flow rate of a dilution gas (typically silane) to 1 time to 6 times the flow rate of a semiconductor source gas (typically hydrogen) at the time of deposition. Thus, a crystal with a three-dimensional shape tapered in a direction of the deposition of a film, i.e., in a direction from the microcrystalline semiconductor layer to the amorphous semiconductor layer is made to grow.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 29, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Satoshi TORIUMI, Tomokazu YOKOI, Makoto FURUNO
  • Publication number: 20090233425
    Abstract: By an evacuation unit including first and second turbo molecular pumps connected in series, the ultimate pressure in a reaction chamber is reduced to ultra-high vacuum. By a knife-edge-type metal-seal flange, the amount of leakage in the reaction chamber is reduced. A microcrystalline semiconductor film and an amorphous semiconductor film are stacked in the same reaction chamber where the pressure is reduced to ultra-high vacuum. By forming the amorphous semiconductor film covering the surface of the microcrystalline semiconductor film, oxidation of the microcrystalline semiconductor film is prevented.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Inventors: Makoto FURUNO, Tetsuo SUGIYAMA, Taichi NOZAWA, Mitsuhiro ICHIJO, Ryota TAJIMA, Shunpei YAMAZAKI
  • Patent number: 7572688
    Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device of which manufacturing process is simplified by improving usage rate of a material.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: August 11, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura
  • Publication number: 20090160753
    Abstract: When semi-amorphous TFTs are used for forming a signal line driver circuit and a pixel, a large amplitude is required for driving the pixel, and a large power supply voltage is thus needed. On the other hand, when a shift register is made up of transistors having a single conductivity, a bootstrap circuit is required, and a voltage over a power supply is applied to a specific element. Therefore, not both the driving amplitude and the reliability can be achieved with a single power supply. According to the invention, a level shifter having a single conductivity is provided to solve such a problem.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 25, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun KOYAMA, Keitaro IMAI, Shinji MAEKAWA, Makoto FURUNO, Osamu NAKAMURA, Shunpei YAMAZAKI
  • Publication number: 20090137087
    Abstract: An object is to provide a film deposition apparatus in which the amount of leakage from the outside of the chamber to the inside of the chamber is reduced. Even if leakage occurs from the outside of the chamber to the inside of the chamber, oxygen and nitrogen included in an atmosphere that surrounds the outer wall of the chamber are reduced as much as possible and the atmosphere is filled with a noble gas or hydrogen, whereby the inside of the chamber is kept cleaner at 1/100 or less, preferably, 1/1000 or less of oxygen concentration and nitrogen concentration than those in the air. Since the space with high airtightness is provided adjacent to the outside of the chamber, the chamber is covered with a bag and a high-purity argon gas is supplied to the bag.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 28, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Makoto Furuno