Patents by Inventor Makoto Furuno

Makoto Furuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7511709
    Abstract: When semi-amorphous TFTs are used for forming a signal line driver circuit and a pixel, a large amplitude is required for driving the pixel, and a large power supply voltage is thus needed. On the other hand, when a shift register is made up of transistors having a single conductivity, a bootstrap circuit is required, and a voltage over a power supply is applied to a specific element. Therefore, not both the driving amplitude and the reliability can be achieved with a single power supply. According to the invention, a level shifter having a single conductivity is provided to solve such a problem.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: March 31, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Shunpei Yamazaki
  • Publication number: 20090081845
    Abstract: A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 26, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Makoto FURUNO
  • Publication number: 20090072237
    Abstract: To provide a method for manufacturing a thin film transistor with excellent electric characteristics and high reliability and a display device including the thin film transistor. A gate insulating film is formed over a gate electrode, crystal nuclei is formed over the gate insulating film using fluorosilane and silane, and crystal growth is generated using the crystal nuclei as nuclei to form a microcrystalline semiconductor film, so that crystallinity at an interface between the gate insulating film and the microcrystalline semiconductor film is improved. Next, a thin film transistor is manufactured using the microcrystalline semiconductor film having crystallinity improved at the interface between the gate insulating film and the microcrystalline semiconductor film as a channel formation region.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 19, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yasuhiro JINBO, Makoto FURUNO
  • Publication number: 20090047760
    Abstract: Electric characteristics of a thin film transistor including a channel formation region including a microcrystalline semiconductor are improved. The thin film transistor includes a gate electrode, a gate insulating film formed over the gate electrode, a microcrystalline semiconductor layer formed over the gate insulating film, a semiconductor layer which is formed over the microcrystalline semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the semiconductor layer. A channel is formed in the microcrystalline semiconductor layer when the thin film transistor is placed in an on state, and the microcrystalline semiconductor layer includes an impurity element for functioning as an acceptor. The microcrystalline semiconductor layer is formed by a plasma-enhanced chemical vapor deposition method.
    Type: Application
    Filed: August 6, 2008
    Publication date: February 19, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Publication number: 20090047759
    Abstract: After a gate insulating film is formed over a gate electrode, in order to improve the quality of a microcrystalline semiconductor film which is formed in an early stage of deposition, a film near an interface with the gate insulating film is formed under a first deposition condition in which a deposition rate is low but the quality of a film to be formed is high, and then, a film is further deposited under a second deposition condition in which a deposition rate is high. Then, a buffer layer is formed to be in contact with the microcrystalline semiconductor film. Further, plasma treatment with a rare gas such as argon or hydrogen plasma treatment is performed before formation of the film under the first deposition condition for removing adsorbed water on a substrate.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 19, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
  • Publication number: 20090047761
    Abstract: An object is to provide a manufacturing method of a microcrystalline semiconductor film with favorable quality over a large-area substrate. After forming a gate insulating film over a gate electrode, in order to improve quality of a microcrystalline semiconductor film formed in an initial stage, glow discharge plasma is generated by supplying high-frequency powers with different frequencies, and a lower part of the film near an interface with the gate insulating film is formed under a first film formation condition, which is low in film formation rate but results in a good quality film. Thereafter, an upper part of the film is deposited under a second film formation condition with higher film formation rate, and further, a buffer layer is stacked on the microcrystalline semiconductor film.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 19, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Sachiaki Teduka, Satoshi Toriumi, Makoto Furuno, Yasuhiro Jinbo, Koji Dairiki, Hideaki Kuwabara
  • Publication number: 20090047758
    Abstract: In a case of forming a bottom-gate thin film transistor, a step of forming a microcrystalline semiconductor film over a gate insulating film by a plasma CVD method, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film are performed. In the step of forming the microcrystalline semiconductor film, the pressure in the reaction chamber is set at or below 10?5 Pa once, the substrate temperature is set in the range of 120° C. to 220° C., plasma is generated by introducing hydrogen and a silicon gas, hydrogen plasma is made to act on a reaction product formed on a surface of the gate insulating film to perform removal while performing film formation. Moreover, the plasma is generated by applying a first high-frequency electric power of an HF band a second high-frequency electric power of a VHF band superimposed on each other.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 19, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Sachiaki TEDUKA, Makoto FURUNO, Satoshi TORIUMI, Yasuhiro JINBO, Koji DAIRIKI
  • Publication number: 20090045401
    Abstract: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor layer which is formed over the gate insulating film and is formed of a microcrystalline semiconductor, a second semiconductor layer which is formed over the first semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the second semiconductor layer are provided in the thin film transistor. A channel is formed in the first semiconductor layer when the thin film transistor is placed in an on state.
    Type: Application
    Filed: August 12, 2008
    Publication date: February 19, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Patent number: 7477216
    Abstract: When a pixel and a signal line driver circuit are made up of semi-amorphous TFTs, an amplitude for driving the pixel has to be made larger, and a high power supply voltage is needed. The high power supply voltage increases power consumption in the case of partial drive. According to the invention, in order to reduce power consumption, a gate signal line driver circuit stores data of whether each gate signal line is used for displaying an image or not, thereby stopping driving of a gate signal line which is not required to be driven.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: January 13, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Shunpei Yamazaki
  • Publication number: 20080296724
    Abstract: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 4, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuhiro Ichijo, Makoto Furuno, Takashi Ohtsuki, Kenichi Okazaki, Tetsuhiro Tanaka, Seiji Yasumoto
  • Publication number: 20070235794
    Abstract: A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more.
    Type: Application
    Filed: March 20, 2007
    Publication date: October 11, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20070235793
    Abstract: It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.
    Type: Application
    Filed: March 20, 2007
    Publication date: October 11, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20070228449
    Abstract: It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 4, 2007
    Inventors: Tamae Takano, Makoto Furuno, Yoshinobu Asami, Shunpei Yamazaki
  • Publication number: 20070228448
    Abstract: It is an object to provide a nonvolatile semiconductor memory device with an excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided. The floating gate has at least a two-layer structure, and a first layer being in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. The stability of the first layer is improved by formation of a second layer of the floating gate electrode using a metal, an alloy, or a metal compound material. Such a structure of the floating gate electrode can improve injectability of carriers in writing and a charge-retention property.
    Type: Application
    Filed: March 20, 2007
    Publication date: October 4, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20070228453
    Abstract: An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided over the semiconductor substrate. The floating gate electrode includes at least two layers. It is preferable that a band gap of a first floating gate electrode, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. It is also preferable that a second floating gate electrode be formed of a metal material, an alloy material, or a metal compound material.
    Type: Application
    Filed: March 20, 2007
    Publication date: October 4, 2007
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20070221971
    Abstract: A semiconductor layer having a channel formation region provided between a pair of impurity regions spaced from each other is provided, and a first insulating layer a floating gate, a second insulating layer, and a control gate are provided above the semiconductor layer. The semiconductor material forming the floating gate preferably has a band gap smaller than that of the semiconductor layer. The band gap of a channel formation region in the semiconductor material forming the floating gate is preferably smaller than that of the semiconductor layer by 0.1 eV or more.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 27, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20070221985
    Abstract: A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 27, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20070212828
    Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device of which manufacturing process is simplified by improving usage rate of a material.
    Type: Application
    Filed: May 4, 2007
    Publication date: September 13, 2007
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura
  • Patent number: 7229862
    Abstract: An object of the present invention is to provide a method for manufacturing a semiconductor device of which manufacturing process is simplified by improving usage rate of a material.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: June 12, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura
  • Patent number: 7211454
    Abstract: The present invention provides an active matrix substrate which can be fabricated at a lower cost and a light emitting device having a large display area fabricated by a vapor deposition system which makes a film with uniform thickness for a large substrate. According to the invention, an organic light-emitting device can be fabricated by performing vapor deposition toward a large substrate provided with a pixel portion (and a driver circuit) including an n-channel TFT having a amorphous silicon film, semi-amorphous semiconductor film or an organic semiconductor film as an active layer.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: May 1, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Masakazu Murakami