Patents by Inventor Makoto Kitabatake

Makoto Kitabatake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6690035
    Abstract: An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: February 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Osamu Kusumoto, Makoto Kitabatake, Takeshi Uenoyama
  • Publication number: 20040022025
    Abstract: Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 5, 2004
    Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Osamu Kusumoto
  • Patent number: 6674131
    Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: January 6, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Makoto Kitabatake, Osamu Kusumoto, Takeshi Uenoyama, Koji Miyazaki
  • Publication number: 20030227061
    Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 11, 2003
    Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
  • Patent number: 6654604
    Abstract: Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 25, 2003
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Osamu Kusumoto
  • Patent number: 6645402
    Abstract: An electron emitting device includes at least a first electrode and an electron emitting section provided on the first electrode. The electron emitting section is formed of a particle or an aggregate of particles. The particle contains a carbon material having a carbon six-membered ring structure. The carbon material having a carbon six-membered ring structure contains, for example, graphite or a carbon nanotube as a main component.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: November 11, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Kurokawa, Tetsuya Shiratori, Masahiro Deguchi, Makoto Kitabatake
  • Patent number: 6635979
    Abstract: An electron emitting device includes at least an electron transporting member (1), an electron emitting member (3), and an electric field concentration region (2) formed between the electron transporting member (1) and the electron emitting member (3). For example, the electron transporting member (1) may be a conductive layer, the electric field concentration region (2) may be formed of an insulating layer formed on the conductive layer, and the electron emitting member (3) may be formed of particles provided on the insulating layer. Due to the electric field concentration in the electric field concentration region (2), electrons are easily injected from the electron transporting member (1) to the electron emitting member (3).
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: October 21, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Shiratori, Hideo Kurokawa, Masahiro Deguchi, Makoto Kitabatake
  • Patent number: 6617653
    Abstract: P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: September 9, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiya Yokogawa, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Takeshi Uenoyama
  • Patent number: 6600203
    Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: July 29, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kunimasa Takahashi, Toshiya Yokogawa, Makoto Kitabatake, Masao Uchida, Osamu Kusumoto, Kenya Yamashita
  • Patent number: 6580125
    Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: June 17, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Patent number: 6577386
    Abstract: An impurity doped SiC substrate 1 and SiC thin film 2 are irradiated with a laser light 5 having a wavelength longer than such a wavelength that a band edge absorption of a semiconductor is caused. The wavelength of the laser light 5 may be such a wavelength that an absorption is caused by a vibration by the bond of an impurity element and an element constituting the semiconductor, for example, a wavelength of 9 &mgr;m to 11 &mgr;m. Specifically, in the case where Al is doped in SiC, the wavelength of the laser light 5 may be within the range of 9.5 &mgr;m to 10 &mgr;m.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: June 10, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihisa Yoshida, Masatoshi Kitagawa, Masao Uchida, Makoto Kitabatake, Tsuneo Mitsuyu
  • Publication number: 20030080384
    Abstract: A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat &dgr;-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 1, 2003
    Applicant: Matsushita Electric Industrial Co.., Ltd.
    Inventors: Kunimasa Takahashi, Masao Uchida, Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Kenya Yamashita, Ryoko Miyanaga
  • Publication number: 20030020136
    Abstract: A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.
    Type: Application
    Filed: August 15, 2002
    Publication date: January 30, 2003
    Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi, Kenya Yamashita
  • Publication number: 20030006415
    Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.
    Type: Application
    Filed: February 26, 2002
    Publication date: January 9, 2003
    Inventors: Toshiya Yokogawa, Kunimasa Takahashi, Makoto Kitabatake, Osamu Kusumoto, Takeshi Uenoyama, Koji Miyazaki
  • Patent number: 6504176
    Abstract: There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: January 7, 2003
    Assignee: Matshushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Masao Uchida, Kunimasa Takahashi
  • Publication number: 20020193039
    Abstract: The first basic structure of the electron emission element of the present invention includes at least two electrodes disposed in a horizontal direction at a predetermined interval, and a plurality of electron emission portions made of a particle or an aggregate of the particles dispersively disposed between the electrodes. On the other hand, the second basic structure of the electron emission element of the present invention includes at least two electrodes disposed at a predetermined interval, a conductive layer disposed between the electrodes so as to be electrically connected thereto, and a plurality of electron emission portions made of a particle or an aggregate of the particles dispersively disposed on the surface of the conductive layer between the electrodes.
    Type: Application
    Filed: July 15, 2002
    Publication date: December 19, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Kurokawa, Tetsuya Shiratori, Toshifumi Sato, Masahiro Deguchi, Makoto Kitabatake
  • Publication number: 20020179909
    Abstract: A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.
    Type: Application
    Filed: June 4, 2002
    Publication date: December 5, 2002
    Inventors: Masao Uchida, Makoto Kitabatake, Toshiya Yokogawa, Osamu Kusumoto, Kunimasa Takahashi, Ryoko Miyanaga, Kenya Yamashita
  • Publication number: 20020158251
    Abstract: A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 31, 2002
    Inventors: Kunimasa Takahashi, Toshiya Yokogawa, Makoto Kitabatake, Masao Uchida, Osamu Kusumoto, Kenya Yamashita
  • Patent number: 6445114
    Abstract: The first basic structure of the electron emission element of the present invention, includes at least two electrodes disposed in a horizontal direction at a predetermined interval, and a plurality of electron emission portions made of a particle or an aggregate of the particles dispersively disposed between the electrodes. On the other hand, the second basic structure of the electron emission element of the present invention includes at least two electrodes disposed at a predetermined interval, a conductive layer disposed between the electrodes so as to be electrically connected thereto, and a plurality of electron emission portions made of a particle or an aggregate of the particles dispersively disposed on the surface of the conductive layer between the electrodes.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: September 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Kurokawa, Tetsuya Shiratori, Toshifumi Sato, Masahiro Deguchi, Makoto Kitabatake
  • Patent number: 6400091
    Abstract: An electron emission element of the present invention includes a substrate, a cathode formed on the substrate, an anode opposed to the cathode, an electron emission member disposed on the cathode, and a control electrode disposed between the cathode and the anode. During operation, the electric field intensity immediately above the electron emission member is lower than that between the control electrode and the anode. Alternatively, the spatial average of an electric field intensity between the electron emission member and the control electrode is smaller than that between the control electrode and the anode.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: June 4, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Deguchi, Makoto Kitabatake, Kanji Imai, Tomohiro Sekiguchi, Hideo Kurokawa, Keisuke Koga, Tetsuya Shiratori, Toru Kawase