Abstract: A semiconductor device includes: a memory cell array having a plurality of memory cells arranged in arrays; a plurality of bit lines formed correspondingly to a column arrangement of the memory cells; a plurality of word lines formed correspondingly to a row arrangement of the memory cells; a plate line having one of a configuration in which the first electrodes of the respective memory cells are included in the plate line and a configuration in which the first electrodes are connected to the plate line; a column switch used to connect a selected bit line and a data access line; and a pre-charge portion that performs a pre-charge operation to pre-charge a non-selected bit line not selected by the column switch to potential of the plate line.

Abstract: A display capable of rendering flickering hard to visually recognize, reducing power consumption and simplifying the structure of a circuit for negatively/positively reversing an image is provided. This display comprises a plurality of drain lines and a plurality of gate lines, a first pixel portion and a second pixel portion each including a subsidiary capacitor having a first electrode and a second electrode and a first subsidiary capacitance line and a second subsidiary capacitance line connected to the subsidiary capacitors of the first pixel portion and the second pixel portion respectively.

Abstract: A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit line switch. The memory-cell array is laid out to form an array. The read bit line is shared by plural memory cells and connected to a data output node. The write bit line is shared by plural memory cells and connected to a data input node. The sense amplifier is configured to sense a difference in electric potential. The first sense line is connected to one of the input terminals. The second sense line is connected to the other input terminal. The first bit line switch is configured to control electrical connection and disconnection. The second bit line switch is configured to control electrical connection and disconnection.

Abstract: A semiconductor device, includes a memory cell including a thyristor element with a gate having a pnpn structure formed on a semiconductor substrate and having first and second terminals, and an access transistor formed on the semiconductor substrate and having first and second terminals connected to a bit line and the first terminal of the thyristor element, respectively, and a control section including a load current element whose load current flows, upon reading out operation, to the second terminal side of the thyristor element and configured to carry out access control to the memory cell.

Abstract: A semiconductor device includes a memory cell including a thyristor element with a gate having a pnpn structure formed in a semiconductor substrate, and a plurality of access transistors formed on the semiconductor substrate and each connected at a first terminal thereof to a storage node at one terminal of the thyristor element such that a potential at the storage node can be transmitted to bit lines different from each other, the gate of the thyristor element and the gates of the plurality of access transistors of the memory cell being connected to word lines different from one another.

Abstract: Disclosed herein is a semiconductor memory device including, a memory array with memory cells array-like arranged, a read bit line connected to a data output node of the memory cells and shared by a plurality of the memory cells arranged in one direction in the memory array, a write bit line connected to a data input node of the memory cells and shared by a plurality of the memory cells, a sense amplifier for sensing a voltage of the reading bit line, a first sense line and a second sense line connected to the sense amplifier, a read bit line switch for controlling electrical connection and disconnection between the first sense line and the read bit line, a write buffer connected between the second sense line and the write bit line, capable of controlling electrical connection and disconnection between the second sense line and the write bit line.

Abstract: A semiconductor memory device includes: a memory cell; a sense line; and a sense amplifier circuit connected to the memory cell via the sense line. The sense amplifier circuit includes a differential sense amplifier, a pull-up section, a read gate transistor, and a threshold correction section.

Abstract: A system infrastructure structure formulation supporting method in which based on quality requirements, formulated examples of system infrastructure structures up to the present are grouped into a database for storing the system infrastructure structures, then being stored into a group management area in advance. At the time of a new formulation, demands presented with an expression which user uses are accepted from an input/output terminal. Then, the demands are converted into quality requirements of the system by making reference to a demand-contents management table, a quality-requirement management table, and a demand-quality-requirement correspondence table stored in a reference information storage area. Next, using the quality requirements acquired, a group stored in the group management area is selected. Moreover, elements within the group are selected from a grouping table, then sequentially presenting the formulated examples having high degrees of similarity.

Abstract: Disclosed herein is a semiconductor memory device including, a memory array with memory cells array-like arranged, a read bit line connected to a data output node of the memory cells and shared by a plurality of the memory cells arranged in one direction in the memory array, a write bit line connected to a data input node of the memory cells and shared by a plurality of the memory cells, a sense amplifier for sensing a voltage of the reading bit line, a first sense line and a second sense line connected to the sense amplifier, a read bit line switch for controlling electrical connection and disconnection between the first sense line and the read bit line, a write buffer connected between the second sense line and the write bit line, capable of controlling electrical connection and disconnection between the second sense line and the write bit line.

Abstract: A semiconductor memory device includes a memory-cell array, a read bit line, a write bit line, a sense amplifier, a first sense line, a second sense line, a first bit line switch, and a second bit line switch. The memory-cell array is laid out to form an array. The read bit line is shared by plural memory cells and connected to a data output node. The write bit line is shared by plural memory cells and connected to a data input node. The sense amplifier is configured to sense a difference in electric potential. The first sense line is connected to one of the input terminals. The second sense line is connected to the other input terminal. The first bit line switch is configured to control electrical connection and disconnection. The second bit line switch is configured to control electrical connection and disconnection.

Abstract: A power supply circuit (300) for a display device such as a liquid crystal outputs a boosted supply voltage VDD2 during normal operation, and generates a non-boosted supply voltage VDD2 having a voltage lower than that during the normal display operation by controlling the switches for switching the output within the power supply circuit (300) during a power save mode. The non-boosted supply voltage is supplied to the analog circuits of a driving circuit (100) so that the power consumption at the analog circuits is reduced. By controlling the switch for switching the output within the power supply circuit and the supply of the power supply clock, the circuit can be switched, in the power save mode, to either a mode where a lower supply voltage is generated or to a mode where the power supply is turned off.

Abstract: A liquid crystal display device has a liquid crystal panel, a DA converter for generating a common electrode signal to be applied to a common electrode of a liquid crystal, and a non-volatile memory for encoding an optimum value of the common electrode signal into an ID code and storing the ID code therein. The DA converter generates the optimum common electrode signal corresponding to the ID code read out from the non-volatile memory. A liquid crystal panel manufacturer ships the liquid crystal panel in which the optimum value of the common electrode signal is encoded into the ID code and stored in the non-volatile memory in an inspecting process. The assembling manufacturer using the liquid crystal panel can easily set the optimum value of the common electrode signal. Furthermore, the liquid crystal display device has a CPU decoding the ID code read out from the non-volatile memory. Alternatively, it is possible to supply a data of a value of the common electrode signal to a user of the liquid crystal.

Abstract: Power consumption in an active matrix type liquid crystal display device having partial display function is reduced. In one frame period, a display area corresponding to first 80 horizontal periods, that is the first line through the 80th line, is set as a partial display area and a display area corresponding to the remaining 239 lines is set as a background display area. And a partial display area control signal ENBSC is set at a low level and an SC inversion drive is performed in the partial display area. The partial display area control signal ENBSC is fixed at a high level in the background display area and all of SC inversion control units corresponding to the background display area halt their operation.

Abstract: A display capable of rendering flickering hard to visually recognize, reducing power consumption and simplifying the structure of a circuit for negatively/positively reversing an image is provided. This display comprises a plurality of drain lines and a plurality of gate lines, a first pixel portion and a second pixel portion each including a subsidiary capacitor having a first electrode and a second electrode and a first subsidiary capacitance line and a second subsidiary capacitance line connected to the subsidiary capacitors of the first pixel portion and the second pixel portion respectively.

Abstract: A mask circuit is provided in a display device having a plurality of pixels. The mask circuit supplies a video signal to each of the pixels in a partial display area selected based on a display area selection signal, and prevents the supply of the video signal to each of the pixels in a background display area. Accordingly, this display device displays an arbitrary pattern at an arbitrary position of the display panel of the display device. In addition, an inverting controlling circuit is provided for inverting the background display signal supplied to each of the pixels in the background display area for each frame. The power consumption of the display device can be reduced.

Abstract: A multiplicity adjustment agent collects request information database from a sub-system including an element of a system to be monitored. An individual sub-system's multiplicity adjustment server sorts and merges request information collected from each sub-system for each element/request path. An integrated multiplicity analysis server calculates a necessary multiplicity on the basis of the request information.

Abstract: This invention is directed to the active matrix display device with an imaging speed rapid enough for the moving image display and the small power consumption. The selector makes the switch between the moving image mode, where the image signal consecutively inputted is consecutively displayed after the certain processing is performed by the data processing unit and the still image mode, where the display is made based on the image signal stored in the frame memory. The messy display upon the switching between the modes can be prevented by differentiating the switching timing of the still to moving image mode from that of the moving to still image mode, improving the display quality.

Abstract: A session-information preserving system includes a client to which business data are inputted and a server which processes the business data sent from the client computer.

Abstract: A driving circuit of a display device such as a liquid crystal generates power supply clocks (1 and 2) based on a system clock during the normal display operation which is not a power save mode. The generated power supply clocks are supplied, directly or after inversion, to the switches (SW1 through SW4 (and SW5 through SW8)) in a charge pump type power supply circuit (300) for switching the connection of capacitors (C1 and C2 (and C11 and C12)) in the power supply circuit (300). In this manner, supply voltages VDD2 and VDD3 which function as the driving power supply for a driving circuit (100) and a display panel (200) can be obtained at the power supply circuit (300) by boosting the input voltage Vin.

Abstract: A liquid crystal display apparatus includes a liquid crystal display panel having preset display characteristics, such as image brightness and contrast. A luminescent unit is optically connected with the display panel and provides light to the display panel in order to form an image on the display panel. The luminescent unit includes a light collector which collects ambient light and a light source, for generating light when the amount of ambient light is insufficient to generate a clear image. A control circuit is electrically connected to the display panel and automatically varies the preset display characteristics in accordance with the amount of ambient light collected by the light collector.