Patents by Inventor Makoto Kitano

Makoto Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5101263
    Abstract: In a plastic encapsulated semiconductor device, a part of wire piece may break down due to thermal fatigue, which positioned adjacent to a bonding portion of the wire piece connected to a chip. This is caused by that wire piece moves relative to plastic encapsulating the chip and the wire piece, and a strain in the wire piece due to thermal deformation of the device concentrates on one portion of the wire piece. Accordingly, a rugged portion is formed on a surface of a part of wire piece subjected to a breakdown to thermal fatigue. The plastic bites recesses of the rugged portion to prevent the wire piece from moving relative to the plastic, thereby preventing the wire piece from breaking down due to thermal fatigue.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: March 31, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Chikako Kitabayashi, Asao Nishimura, Hideo Miura, Akihiro Yaguchi, Sueo Kawai
  • Patent number: 5068712
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: September 19, 1989
    Date of Patent: November 26, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 5047837
    Abstract: A packaged semiconductor device having heat transfer leads carrying a semiconductor chip directly or indirectly through a chip pad and extended to the exterior of the plastic or ceramics seal of the package, and a heat transfer cap held in surface contact with the extended heat transfer leads and covering upper side of the package. The heat generated in the semiconductor chip is transmitted to the upper side of the package and to the printed circuit board only through metallic parts so that the heat transfer is enhanced to remarkably reduce thermal resistance, thus enabling packaging of a semiconductor chip having a large heat generation rate.
    Type: Grant
    Filed: August 3, 1989
    Date of Patent: September 10, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Takahiro Daikoku, Sueo Kawai, Ichio Shimizu, Kazuo Yamazaki, Asao Nishimura, Hideo Miura, Akihiro Yaguchi
  • Patent number: 5041901
    Abstract: A lead frame having a plurality of inner leads and outer leads, said outer leads being subjected to surface treatment for improving solder wettability at an end portion and to sruface treatment for suppressing solder wettability at least at a portion neighboring to the end portion, or said outer leads being bent 4 times or more, is effective for improving thermal fatigue life and reliability when applied to a semi-conductor device.
    Type: Grant
    Filed: May 2, 1990
    Date of Patent: August 20, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai, Akio Hoshi, Ichio Shimizu
  • Patent number: 4987474
    Abstract: In a tabless lead frame wherein a space for laying inner leads is sufficiently secured when a lengthened and enlarged semiconductor pellet is placed or set in a resin-molding package, through holes are provided in leads for the purpose of increasing the occupation area ratio of a resin portion. Furthermore, each of the leads corresponding to the lower surface of the pellet is branched into a plurality of portions in the widthwise direction thereof in order to reduce a stress. Further, in an insulating sheet which is interposed between the leads and the pellet, the dimension of the shorter lateral sides thereof is set smaller than that of the shorter lateral sides of the pellet in order to prevent cracks from occurring at the end part of the insulating sheet.
    Type: Grant
    Filed: June 12, 1990
    Date of Patent: January 22, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Yasuhara, Masachika Masuda, Asao Nishimura, Naozumi Hatada, Sueo Kawai, Makoto Kitano, Hideo Miura, Akihiro Yaguchi, Gen Murakami
  • Patent number: 4942452
    Abstract: A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.
    Type: Grant
    Filed: February 22, 1988
    Date of Patent: July 17, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Sueo Kawai, Asao Nishimura, Hideo Miura, Akihiro Yaguchi, Chikako Kitabayashi, Ichio Shimizu, Toshio Hatsuda, Toshinori Ozaki, Toshio Hattori, Souji Sakata