Patents by Inventor Makoto Kitano

Makoto Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5637914
    Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: June 10, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Naotaka Tanaka, Akihiro Yaguchi, Makoto Kitano, Tatsuya Nagata, Tetsuo Kumazawa, Atsushi Nakamura, Hiromichi Suzuki, Masayoshi Tsugane
  • Patent number: 5635756
    Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependent on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: June 3, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura
  • Patent number: 5621243
    Abstract: A high reliability electric power control semiconductor device with a prolonged product lifetime has been provided by successfully suppressing the metal support plate or the metal heat dissipation plate from warping due to the thermal stress during bonding so as to prevent the occurrences of cracks and gaps in the brazing fillers in the bonded layers between the metal heat dissipation plate or the metal support plate and the insulation plate in the semiconductor device comprising the semiconductor elements, metal heat dissipation plate, thermal stress buffer, insulation plate, and the metal support plate, wherein at least one of the metal heat dissipation plate and the metal support plate comprises a copper alloy of which a softening temperature at which a hot hardness of which becomes 1/2 of the hardness at the room temperature is 350.degree. C. or more.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: April 15, 1997
    Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.
    Inventors: Noboru Baba, Hisanori Okamura, Masahiko Sakamoto, Hirosi Akiyama, Ryuichi Saito, Yoshihiko Koike, Makoto Kitano, Sigeki Sekine, Hideya Kokubun, Nobuya Koike
  • Patent number: 5612569
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: March 18, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 5608265
    Abstract: A semiconductor device, provided in a plastic encapsulated package, having a semiconductor chip, a lead and a member for electrically connecting them together. The semiconductor device has one or more first holes respectively extending from one surface of the package to a first side of the lead which is provided inside of the package, and has one or more second holes formed which are aligned with the first holes, respectively, in a manner such that each second hole is extended from the opposing surface of the package to a corresponding location on a second side of the lead and is aligned with a corresponding, opposing first hole, in the package, extending to the first side of the lead. These holes are provided as a plurality of sets of individual pairs of aligned holes respectively extending inwardly, from opposing surfaces of the package, to opposite sides of the corresponding leads.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: March 4, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Naotaka Tanaka, Tetsuo Kumazawa
  • Patent number: 5569960
    Abstract: An electronic component unit is provided with two electronic components which are disposed in parallel with each other and each of which has an internal electric circuit therein. Electrode pads are provided on the opposed surfaces of the two electronic components and are electrically connected to the internal electric circuits. The pads on one of the electronic components are respectively electrically and mechanically connected to the corresponding pads on the other electronic component by solder bumps. The areas of the pads increase or decrease stepwise in the direction from the central portions toward the outer peripheral edges of the two electronic components, while the volumes of the solder bumps are constant. Alternatively, the volumes of the solder bumps decrease or increase in the direction from the central portions toward the outer peripheral edges of the two electronic components, while the areas of all pads are constant.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: October 29, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Kumazawa, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Naotaka Tanaka, Nae Yoneda, Ichiro Anjoh
  • Patent number: 5539250
    Abstract: A plastic-molded-type semiconductor device is provided wherein two semiconductor chips, having main surfaces on which electrodes and circuits are formed, are arranged to face each other. A lead frame is placed between these two semiconductor chips and electrically connected to their electrodes, and a plastic package is formed by plastic-sealing the above components. To provide for secure and convenient electrical connections between the electrodes on the semiconductor chips and the lead frame, wiring patterns are provided on the main surfaces of the semiconductor chips through the intermediation of insulating films. With this structure, it is possible for two large-sized semiconductor chips having electrodes in their middle sections to be encased in a single, relatively thin package.
    Type: Grant
    Filed: June 11, 1991
    Date of Patent: July 23, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda
  • Patent number: 5530286
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: June 25, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 5488254
    Abstract: A plastic-molded-type semiconductor device is designed to prevent interfaces of a heat conductive member for heat radiation and plastic encapsulant from being separated from each other. The device is of a structure in which the heat conductive member for heat radiation is provided on and thermally connected to one side of a semiconductor chip, and the whole chip and the whole or a part of side surfaces of the heat conductive member are covered with the resin, the opposite side of the heat conductive member being exposed. In this structure, that portion of the heat conductive member which is covered with the resin has a cross-section whose configuration is any one of a circle, an ellipse, a polygon with corner portions whose internal angle is less than 180 degrees and a dull angle or which are rounded to have a low curvature.
    Type: Grant
    Filed: March 29, 1994
    Date of Patent: January 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Asao Nishimura, Makoto Kitano, Ichio Shimizu
  • Patent number: 5391916
    Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependence on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura
  • Patent number: 5358904
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: October 25, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjoh, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: 5357139
    Abstract: In a package for DRAM, plastic is included between the common signal inner leads (bus bar inner leads) and insulating films arranged in the central part of a semiconductor chip. Thus, the deformation of plastic at the upper edge of the common signal inner leads is reduced and no great stress is generated at this portion. Accordingly, plastic cracking can be prevented.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: October 18, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
  • Patent number: 5347429
    Abstract: A plastic-molded-type semiconductor device includes a plurality of semiconductor chips, metallic wires connected to the semiconductor chips, leads connected to the metallic wires, and an insulating member interposed between the semiconductor chips and sealed in a resin member. Circuit formed surfaces of the semiconductor chips are directed in the same direction, and one or more of the semiconductor chips serve as a base on which the other semiconductor chips are mounted through the insulating member. One ends of the leads are bonded to the insulating member, and electrodes pad of each semiconductor chip are not covered by the other semiconductor chips, the insulating member and the leads, and therefore are exposed to the surface of the insulating member. In this device, the provision of a tab is omitted, and the laminated chips can be contained in a package thinner than a conventional package.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: September 13, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda
  • Patent number: 5299092
    Abstract: A plastic sealed type semiconductor apparatus includes at least two semiconductor devices which are disposed with a space therebetween in such a manner that circuit forming surfaces oppose each other, and an electric signal lead which is adhered to each of the circuit forming surfaces with an insulating member provided therebetween for electric insulation and which is electrically connected to the semiconductor device by a thin metal wire. The semiconductor devices and the electric signal leads are sealed with a resin in a state where the electric signal leads are laid on top of one another to form a plastic package. The overlaid portion of the electric signal leads has a surface contact portion of the leads and a resin providing portion. The resin providing portion is a recessed portion which is formed when the resin is molded in such a manner that it passes through the surface contact portion of the leads in the lateral direction thereof.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: March 29, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Yaguchi, Asao Nishimura, Makoto Kitano, Ichiro Anjoh, Junichi Arita
  • Patent number: 5296737
    Abstract: A semiconductor device comprises a plurality of semiconductor chips; electrodes formed on circuit surfaces of said plurality of semiconductor chips; inner leads made of a metal foil and bonded at first ends thereof to the electrodes, outer leads each having a predetermined surface at a first end thereof bonded to a second end of at least one of the inner leads, and a sealing material sealing said plurality of semiconductor chips, the electrodes, the inner leads, and part of each of the outer leads. The semiconductor chips are laminated in such a manner that those surfaces of the semiconductor chips on which their respective circuits are formed are disposed in facing relation to each other. This provides a semiconductor device which is excellent in assembling efficiency.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: March 22, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Gen Murakami, Ichiro Anjoh
  • Patent number: 5295045
    Abstract: A plastic-molded-type semiconductor device having a high degree of integration encases a plurality of semiconductor chips in a package unit with each chip situated perpendicular to the substrate for mounting. On a surface of each chip containing circuits or on a reverse surface of the same, a lead frame is attached with an insulating material interposed therebetween. The chip and lead frame are connected with each other by using wire. The lead frame is arranged perpendicularly to another lead frame provided in parallel and connected therewith by welding. A printed circuit board may be used in place of said latter lead frame. By arranging the chips in projections made of resin, the thermal resistance of the semiconductor device is decreased. The present invention is particularly effective for a memory IC.
    Type: Grant
    Filed: November 14, 1991
    Date of Patent: March 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Maya Obata, Ryuji Kohno, Mitsuaki Haneda
  • Patent number: 5293068
    Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conducting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: March 8, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai
  • Patent number: 5256903
    Abstract: A plastic encapsulated semiconductor device containing one or more of insulating films. Uneven surfaces, such as recesses and roughened surfaces, are strategically provided on peripheral side (edge) surfaces of the insulating films. As a result, therefore, an interface separation does not easily occur between the side surfaces of the insulating films and the encapsulating resin. If such an interface separation should occur, it cannot develop easily. Thus, it is possible to obtain a plastic encapsulated semiconductor device of a high level of reliability even when the largest possible semiconductor element is mounted therein within limited outside dimensions.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: October 26, 1993
    Assignee: Hitachi Ltd.
    Inventors: Maya Obata, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Ryuji Kohno, Nae Yoneda, Ichiro Anjoh, Gen Murakami
  • Patent number: 5194935
    Abstract: The plastic encapsulated semiconductor device according to the present invention has a semiconductor chip, leads, and members for electrically connecting these parts to each other. A part of leads, the semiconductor chip and the connecting members are encapsulated with a plastic to form a package. The plate type plastic fins formed on the surface of and integrally with the package are divided in two directions perpendicular to each other thereby forming, for example, rows and columns of fins or fin segments, on the package surface. Therefore, the semiconductor device according to the present invention can be molded easily by a transfer molding. It has a high reliability with respect to the prevention of cracks in the plastic, and a low thermal resistance, and is most suitably used to obtain a high-density package mounting structure.
    Type: Grant
    Filed: January 29, 1991
    Date of Patent: March 16, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Nae Yoneda, Ryuji Kohno, Sueo Kawai, Gen Murakami, Ichio Shimizu
  • Patent number: 5159434
    Abstract: An encapsulated semiconductor device has a chip, a chip pad having through holes and also conducting patterns corresponding to an electrode pad of the chip, and leads. An arbitrary external terminal arrangement is obtained by combining a wire bonding operation between the conduting pattern and lead. Wire bonding is advantageously performed between the leads and electrode pads of the semiconductor chip arranged at arbitrary positions. The degree of freedom in designing areas of the chips and also a printed circuit board is improved so that a high packaging density is achieved and furthermore the printed circuit board is made compact.
    Type: Grant
    Filed: February 1, 1991
    Date of Patent: October 27, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Makoto Kitano, Asao Nishimura, Akihiro Yaguchi, Sueo Kawai