Patents by Inventor Makoto Kudo

Makoto Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7340587
    Abstract: An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: March 4, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Makoto Kudo
  • Publication number: 20080010541
    Abstract: An integrated circuit device (or a microcomputer) including a CPU, a fixed value input terminal, a fixed value holding section which receives a signal input through the fixed value input terminal and holds a fixed value when a reset signal is set at a first level; and a control section which controls the fixed value not to change when the reset signal is set at a second level.
    Type: Application
    Filed: May 18, 2007
    Publication date: January 10, 2008
    Inventor: Makoto Kudo
  • Patent number: 7223993
    Abstract: In the semiconductor laser or electro-absorption optical modulator that includes strained quantum well layers as active layers, making laser characteristics or modulator characteristics adequate has seen the respective limits since band structures, especially, ?Ec and ?Ev, have been unable to be adjusted independently. This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier layers each having strain of an opposite sign to the strain applied to the quantum well layers.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: May 29, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Kouji Nakahara, Makoto Kudo, Shigehisa Tanaka, Masataka Shirai
  • Publication number: 20070051939
    Abstract: In the semiconductor laser or electro-absorption optical modulator that includes strained quantum well layers as active layers, making laser characteristics or modulator characteristics adequate has seen the respective limits since band structures, especially, ?Ec and ?Ev, have been unable to be adjusted independently. This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier layers each having strain of an opposite sign to the strain applied to the quantum well layers.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 8, 2007
    Inventors: Kouji Nakahara, Makoto Kudo, Shigehisa Tanaka, Masataka Shirai
  • Publication number: 20060218445
    Abstract: An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.
    Type: Application
    Filed: February 20, 2006
    Publication date: September 28, 2006
    Inventor: Makoto Kudo
  • Publication number: 20060218383
    Abstract: An integrated circuit device having a CPU which performs given processing based on an instruction code, and a coprocessor which performs given calculation processing based on data supplied from the CPU and outputs a calculation result to the CPU. The CPU includes an immediate value generation section which generates immediate data imm based on the instruction code and outputs the generated immediate data, and an immediate data supply line IMC used to supply the immediate data imm output from the immediate value generation section to the coprocessor.
    Type: Application
    Filed: March 10, 2006
    Publication date: September 28, 2006
    Inventor: Makoto Kudo
  • Publication number: 20060218378
    Abstract: An integrated circuit device including: a CPU which executes given processing based on an instruction code; an instruction code bus used to supply an instruction code to the CPU from a memory; and an instruction code supply line used to supply an instruction code output from a coprocessor to the CPU. The CPU includes: a fetch section which fetches an instruction code; and an instruction code select circuit which receives an instruction code input through the instruction code bus and an instruction code supplied through the instruction code supply line, and supplies one of the instruction codes to the fetch section.
    Type: Application
    Filed: March 24, 2006
    Publication date: September 28, 2006
    Inventor: Makoto Kudo
  • Patent number: 7114101
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: September 26, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Publication number: 20060206763
    Abstract: A debugging system, comprising a pin-saving type debug tool and a target system to be a debug target of the debug tool, the target system includes: an integrated circuit device incorporating a CPU and an inner debug module, the inner debug module having a function to carry out asynchronous communication with the pin-saving type debug tool thereby to carry out on-chip debugging, wherein the integrated circuit device includes a first clock generation circuit; and a first asynchronous-communication control circuit that carries out communication control for carrying out transmission and reception of debug data to/from the pin-saving type debug tool, through asynchronous type serial data transmission, with a clock generates in a first clock generation circuit being as an operation clock, and wherein the pin-saving type debug tool includes a second clock generation circuit that generates a clock with the same baud rate as that of the first clock generation circuit; and a second asynchronous-communication control ci
    Type: Application
    Filed: February 8, 2006
    Publication date: September 14, 2006
    Inventor: Makoto Kudo
  • Patent number: 7100086
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: August 29, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Publication number: 20060190787
    Abstract: A debugging system that includes a debugging tool in a small pin count package and a target system that is a debugging object of the debugging tool, wherein the substrate of the target system includes an integrated circuit device with a built-in CPU and a communicator for generating and outputting a digital clock, and the integrated circuit device includes an internal debugging module having an on-chip debugging feature for conducting clock synchronous communication with the debugging tool in a small pin count package and a clock input terminal for inputting a clock necessary to conduct clock synchronous communication with the debugging tool in a small pin count package, and the substrate includes a clock output terminal that can be connected to the debugging tool in a small pin count package, wherein the digital clock signal that is outputted from the communicator is outputted outside via the clock output terminal placed on the substrate and is supplied to the inside of the integrated circuit device via the
    Type: Application
    Filed: December 21, 2005
    Publication date: August 24, 2006
    Inventor: Makoto Kudo
  • Patent number: 7065678
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 20, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Patent number: 7047443
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code of a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM> The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 16, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Patent number: 7017069
    Abstract: A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by ½, ¼, 2/4 or ¾ clock period.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: March 21, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Katsuya Iida
  • Publication number: 20050278515
    Abstract: An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.
    Type: Application
    Filed: June 9, 2005
    Publication date: December 15, 2005
    Inventor: Makoto Kudo
  • Patent number: 6954878
    Abstract: A microcomputer 11 with a debug circuit 11b implemented therein for realizing an on-chip debugging function is mounted on a target board 10 in which a variety of buses 15 are led out and connected to a break board 30. The break board 30 is provided with a break condition storage section 31 and a break signal generation section 32. Break conditions are written in the break condition storage section 31 from the side of a debugger 20 through the debug circuit 11b, the CPU 11a and the various buses 15. Then, a user program stored in a ROM 12 is executed. The break signal generation section 32 monitors signals on the various buses 15, and outputs a break generation signal 30a when the signals on the various buses 15 coincide with the break condition. The execution of the user program is interrupted (stopped) based on the break generation signal 30a.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: October 11, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Makoto Kudo
  • Patent number: 6922795
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: July 26, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Publication number: 20050102579
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Application
    Filed: November 12, 2004
    Publication date: May 12, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Publication number: 20050097401
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code of a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM> The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 5, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Patent number: 6885255
    Abstract: The invention saves power by supplying minimum clocks required for respective blocks. In a clock control system that supplies clocks to a plurality of blocks, such as a CPU-4, a bus, a peripheral circuit and other circuits, a clock supplied from a clock oscillator is supplied to clock control sections that are connected to the blocks, respectively. The clock is converted by the clock control sections into clocks with minimum clock numbers required to operate the blocks, respectively, and supplied to the blocks.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: April 26, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Keisuke Hashimoto