Abstract: An on-vehicle control device mounted on a vehicle and controlling traveling of the vehicle includes a vehicle position error specifying unit that estimates a position error of the vehicle, a travel control continuity information determination unit that determines information relating to continuity of a travel control state of the vehicle based on the position error of the vehicle estimated by the vehicle position error specifying unit, and a travel control continuity information output unit that outputs the information relating to the continuity of the travel control state of the vehicle determined by the travel control continuity information determination unit.

Abstract: The present invention provides a speech processing device with which it is possible to achieve smooth communication between the passengers of a host vehicle and the passengers of a desired vehicle. In a communication system according to the present invention, a first communication device 10 transmits the position of a first vehicle Mc, the speech of a speaker 601, and a direction d of utterance to multiple unspecified second vehicles Mr in the surroundings of the first vehicle Mc. A second communication device 10 processes the speech in a sound field formed inside the second vehicles Mr by a speaker array comprising a plurality of speakers 41 so that the virtual sound source of the speech is formed in the direction of the position of the first vehicle Mc, and outputs the processed speech using the speaker array at a sound volume calculated on the basis of the position of the first vehicle Mc, the positions of the second vehicles Mr, and the direction d of utterance of the speaker in the first vehicle Mc.

Abstract: An object of the present invention is to reduce a pitch of selection transistors to select two directions in a semiconductor substrate surface of a three-dimensional vertical semiconductor storage device to reduce a dimension in the semiconductor substrate surface. Gates of selection transistors extending in the same direction are formed by a different process for every other gate, so that the thickness of channel semiconductor layers of the selection transistors can be reduced to almost the same thickness of the thickness of an inversion layer while the channel semiconductor layers and an electrode are contacted over a wide area. On/off control can be executed independently on the channel semiconductor layers formed at two sidewalls of the gates of the selection transistors formed at a pitch of 2F. As a result, dimensions of two directions in the semiconductor substrate surface can be set to 2F without generating double selection.

Abstract: A robot includes a force detection unit and an arm including an end effector. The arm applies a force acting in a predetermined direction to a first workpiece so that the first workpiece is pressed against at least a first surface and a second surface of a second workpiece.

Abstract: A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.

Abstract: A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.

Abstract: An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.

Abstract: An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.

Abstract: The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues. A prefix instruction decoder circuit performs a decode processing only on a prefix instruction. The prefix instruction decoder circuit receives the instruction code before decoding, judges whether or not the instruction is a given prefix instruction, and causes a target instruction to modify an information register to store information necessary for decoding a target instruction when the instruction is the given prefix instruction. A decoder circuit receives each of the instruction codes of the instructions other than the prefix instruction as a decode instruction and decodes the decode instruction. When the decode instruction is a target instruction, the target instruction modified by the prefix instruction is decoded based on the target instruction modifying information.

Abstract: An integrated circuit device (or a microcomputer) including a CPU, a fixed value input terminal, a fixed value holding section which receives a signal input through the fixed value input terminal and holds a fixed value when a reset signal is set at a first level; and a control section which controls the fixed value not to change when the reset signal is set at a second level.

Abstract: In the semiconductor laser or electro-absorption optical modulator that includes strained quantum well layers as active layers, making laser characteristics or modulator characteristics adequate has seen the respective limits since band structures, especially, ?Ec and ?Ev, have been unable to be adjusted independently. This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier layers each having strain of an opposite sign to the strain applied to the quantum well layers.

Abstract: In the semiconductor laser or electro-absorption optical modulator that includes strained quantum well layers as active layers, making laser characteristics or modulator characteristics adequate has seen the respective limits since band structures, especially, ?Ec and ?Ev, have been unable to be adjusted independently. This invention is constructed by stacking an n-type InGaAlAs-GRIN-SCH layer 3, an MQW layer 4, a p-type InGaAlAs-GRIN-SCH layer 5, a p-type InAlAs electron-stopping layer 6, and others, in that order, on an n-type InP wafer 1; wherein the MQW layer 4 includes InGaAlAs-strained quantum well layers and InGaAlAsSb-formed barrier layers each having strain of an opposite sign to the strain applied to the quantum well layers.

Abstract: An integrated circuit device having a CPU which performs given processing based on an instruction code, and a coprocessor which performs given calculation processing based on data supplied from the CPU and outputs a calculation result to the CPU. The CPU includes an immediate value generation section which generates immediate data imm based on the instruction code and outputs the generated immediate data, and an immediate data supply line IMC used to supply the immediate data imm output from the immediate value generation section to the coprocessor.

Abstract: An integrated circuit device including: a CPU which executes given processing based on an instruction code; an instruction code bus used to supply an instruction code to the CPU from a memory; and an instruction code supply line used to supply an instruction code output from a coprocessor to the CPU. The CPU includes: a fetch section which fetches an instruction code; and an instruction code select circuit which receives an instruction code input through the instruction code bus and an instruction code supplied through the instruction code supply line, and supplies one of the instruction codes to the fetch section.

Abstract: An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.

Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.

Abstract: A debugging system, comprising a pin-saving type debug tool and a target system to be a debug target of the debug tool, the target system includes: an integrated circuit device incorporating a CPU and an inner debug module, the inner debug module having a function to carry out asynchronous communication with the pin-saving type debug tool thereby to carry out on-chip debugging, wherein the integrated circuit device includes a first clock generation circuit; and a first asynchronous-communication control circuit that carries out communication control for carrying out transmission and reception of debug data to/from the pin-saving type debug tool, through asynchronous type serial data transmission, with a clock generates in a first clock generation circuit being as an operation clock, and wherein the pin-saving type debug tool includes a second clock generation circuit that generates a clock with the same baud rate as that of the first clock generation circuit; and a second asynchronous-communication control ci

Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.

Abstract: A debugging system that includes a debugging tool in a small pin count package and a target system that is a debugging object of the debugging tool, wherein the substrate of the target system includes an integrated circuit device with a built-in CPU and a communicator for generating and outputting a digital clock, and the integrated circuit device includes an internal debugging module having an on-chip debugging feature for conducting clock synchronous communication with the debugging tool in a small pin count package and a clock input terminal for inputting a clock necessary to conduct clock synchronous communication with the debugging tool in a small pin count package, and the substrate includes a clock output terminal that can be connected to the debugging tool in a small pin count package, wherein the digital clock signal that is outputted from the communicator is outputted outside via the clock output terminal placed on the substrate and is supplied to the inside of the integrated circuit device via the

Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].