Patents by Inventor Makoto Kudo

Makoto Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6560692
    Abstract: The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient description of processes that save and restore the contents of registers, increasing the speed of processing of interrupts and subroutine calls and returns. A CPU that uses this data processing circuit comprises a dedicated stack pointer register SP and uses an instruction decoder to decode a group of dedicated stack pointer instructions that specify the SP as an implicit operand. This group of dedicated stack pointer instructions are implemented in hardware by using general-purpose registers, the PC, the SP, an address adder, an ALU, a PC incrementer, internal buses, internal signal lines, and external buses.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: May 6, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Satoshi Kubota, Yoshiyuki Miyayama, Hisao Sato
  • Patent number: 6553506
    Abstract: An objective is to provide information processing device and electronic equipment that is capable of transferring data rapidly while using start-stop synchronization. A communication section (142) comprised within a microcomputer (140) comprises a frequency division circuit (146) that divides a BCLK signal to generate an SMC1 signal (a clock signal for sampling each bit of data sent by start-stop synchronization) and a send/receive circuit (144) for transmitting data based on SMC1. The communication section (142) supplies the BCLK signal to a debugging tool (150) as a signal for enabling a frequency division circuit (156) to generate another signal SMC2. A division ratio control section (158) changes a division ratio FD2 in accordance with the frequency of BCLK and transfers division ratio data to the communication section (142), and the division ratio control section (148) changes a division ratio FD1 in the frequency division circuit (146) based on this division ratio data.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: April 22, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yoichi Hijikata, Makoto Kudo
  • Publication number: 20030062538
    Abstract: A semiconductor device with improved heat radiation characteristics that is formed by employing a lattice-mismatched system semiconductor thin-film crystal layered product. In fabricating an HBT on a semi-insulating GaAs substrate, the HBT comprised of a material system lattice-matched to InP that is different from the substrate in the lattice constant, a structure is employed that comprises alloy compound semiconductor layers with thermal resistivities that increase with increasing lattice constant (e.g., InxGa1−xAs) and alloy compound semiconductor layers with thermal resistivities that decrease with increasing lattice constant (e.g., InyGa1−yP) as a lattice-strain-relaxed buffer layer. By using the above-mentioned lattice-strain-relaxed buffer layer, the thermal resistivity of the buffer layer can be reduced compared to a lattice-strain-relaxed buffer layer consisting of only InxGa1−xAs materials and a lattice-strain-relaxed buffer layer consisting of only InyGa1−yP materials.
    Type: Application
    Filed: May 15, 2002
    Publication date: April 3, 2003
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tohru Oka, Tomoyoshi Mishima
  • Publication number: 20020176465
    Abstract: In a semiconductor laser for emitting light perpendicular to substrate crystal, including, on the substrate crystal, an active layer for generating light, a cavity structure sandwiching the active layer by reflecting mirrors so as to obtain a laser beam from the light generated from the active layer, and a regrown semiconductor layer between the active layer and one of the reflecting mirrors, a regrown interface or a face very close to the regrown interface is formed by a thin film containing dopants of high concentration. With the configuration, an adverse influence of a contamination deposit on the regrown interface is eliminated by delta-doping the regrown interface. The cost is reduced and device resistance is also reduced to 50 &OHgr; or less. Thus, an edge emitting laser (VCSEL) for realizing a optical module achieving a high speed characteristic over 10 Gb/s is obtained.
    Type: Application
    Filed: May 28, 2002
    Publication date: November 28, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Masahiko Kondow, Takeshi Kitatani, Makoto Kudo
  • Publication number: 20020091494
    Abstract: A microcomputer 11 with a debug circuit 11b implemented therein for realizing an on-chip debugging function is mounted on a target board 10 in which a variety of buses 15 are led out and connected to a break board 30. The break board 30 is provided with a break condition storage section 31 and a break signal generation section 32. Break conditions are written in the break condition storage section 31 from the side of a debugger 20 through the debug circuit 11b, the CPU 11a and the various buses 15. Then, a user program stored in a ROM 12 is executed. The break signal generation section 32 monitors signals on the various buses 15, and outputs a break generation signal 30a when the signals on the various buses 15 coincide with the break condition. The execution of the user program is interrupted (stopped) based on the break generation signal 30a.
    Type: Application
    Filed: December 19, 2001
    Publication date: July 11, 2002
    Inventor: Makoto Kudo
  • Patent number: 6308258
    Abstract: A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyses the thus-input instruction code and performs the processing necessary for the execution of that instruction. The data processing circuit comprises an instruction decoder section, a register file, and an instruction execution section that executes the instruction based on operational details of the instruction analyzed by the instruction decoder section. The instruction decoder section comprises an ext instruction processing section that processed the expansion of immediate data from the prefix instruction.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: October 23, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Kubota, Makoto Kudo, Yoshiyuki Miyayama
  • Publication number: 20010023944
    Abstract: There is disclosed a photodetector which is capable of attaining an enhanced detection accuracy, and at the same time permits reduction in the size and manufacturing costs thereof. An avalanche photodiode detects an incident light, in a state of a predetermined bias voltage set thereto. A cooler cools the avalanche photodiode to a predetermined cooling temperature. An amount of an incident signal light incident on the avalanche photodiode is detected based on a detection signal from the avalanche photodiode. A control block adjusts at least one of the bias voltage and the predetermined cooling temperature, thereby holding a value of the detection signal from the avalanche photodiode generated in a state of the incident light being blocked from impinging on the avalanche photodiode, within a predetermined tolerance range.
    Type: Application
    Filed: March 21, 2001
    Publication date: September 27, 2001
    Applicant: Hioki Denki Kabushiki Kaisha
    Inventors: Tomoyuki Maruyama, Makoto Kudo, Fumio Narusawa
  • Patent number: 6233596
    Abstract: An objective of this invention is a design that improves the memory usage ratio and execution speed of a sum-of-products operation instruction, improves the critical path of sum-of-products operations, and prevents overflows. A sum-of-products operation circuit executes sum-of-products operations a number of times that is specified by number-of-executions information comprised within a sum-of-products operation instruction, under the control of a control circuit. The number of times the sum-of-products operation is to be executed is set into a register, that number is decremented every time one cycle of the sum-of-products operation ends, and the sum-of-products operation instruction ends when the value in the register reaches zero. If an interrupt is received during the execution of a plurality of sum-of-products operations, execution of the sum-of-products operations resumes after the interrupt processing. First and second sum-of-products input data are read at the same time by a single memory access.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 15, 2001
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Kubota, Makoto Kudo, Yoshiyuki Miyayama
  • Patent number: 6167505
    Abstract: A certain target instruction and a prefix instruction for expanding the function of that target instruction are input to the present data processing circuit. The data processing circuit analyzes the thus-input instruction code and performs the processing necessary for the execution of that instruction. The data processing circuit comprises an instruction decoder section, a register file, and an instruction execution section that executes the instruction based on operational details of the instruction analyzed by the instruction decoder section. The instruction decoder section comprises an ext instruction processing section that processed the expansion of immediate data from the prefix instruction.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: December 26, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Satoshi Kubota, Makoto Kudo, Yoshiyuki Miyayama
  • Patent number: 5633516
    Abstract: A semiconductor device has a lattice-mismatched crystal structure including a semiconductor film formed on a substrate with an intervening buffer layer. The buffer layer has a plurality of layers, including first sublayers, or regions, in which an element that controls the lattice constant is provided in increasing mole fraction, and second sublayers, or regions, in which the lattice constant is maintained. The first sublayers and second sublayers are provided in alternating fashion. The resulting device has an increased electron mobility as compared with the prior art.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: May 27, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyoshi Mishima, Katsuhiko Higuchi, Mitsuhiro Mori, Makoto Kudo, Chushiro Kusano
  • Patent number: 5548138
    Abstract: In a semiconductor device using tunnel current and a barrier layer, arrangements are provided to lower the resistance of the semiconductor device. In particular, arrangements are provided to lower the parasitic resistance of a device such as a field effect transistor or an HBT, as well as to provide high-performance low noise amplifiers, mixers and the like using such reduced resistance semiconductor devices. To achieve this reduced resistance, carrier concentration or effective mass is designed not to be uniform in at least one of the semiconductor layers holding a barrier layer therebetween. For example, in an area near the barrier layer, the carrier concentration distribution can be large or the effective mass distribution can be small.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: August 20, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takuma Tanimoto, Makoto Kudo, Tomoyoshi Mishima, Akishige Nakajima, Mitsuhiro Mori, Masao Yamane
  • Patent number: 5495115
    Abstract: A semiconductor crystalline laminate structure wherein between a first semiconductor layer consisting of a first alloyed semiconductor and a second semiconductor layer which has an energy gap wider than that of the first alloyed semiconductor and a lattice constant smaller than that of the first alloyed semiconductor and consists of one semiconductor selected from a group of single-element semiconductor, compound semiconductor, and alloyed semiconductor which contain no semiconductor having a largest lattice constant among the semiconductor constituting the first alloyed semiconductor, a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of the first alloyed semiconductor and contains the semiconductor having a largest lattice constant among the semiconductors constituting the first alloyed semiconductor is formed in contact with these layers, a forming method for the semiconductor crystalline laminate structure, and a semiconductor device using the
    Type: Grant
    Filed: August 8, 1994
    Date of Patent: February 27, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kudo, Tomoyoshi Mishima, Takuma Tanimoto, Misuzu Sagawa
  • Patent number: 3973965
    Abstract: A color cathode ray tube provided with a fluorescent screen formed on the inner surface of the face plate of the envelope and comprising a plurality of stripes of phosphor elements, and a shadow mask formed with a plurality of slit apertures corresponding to the stripes of the phosphor element. Said slit apertures are spaced apart by transverse bridge members. Each slit aperture is surrounded by inclined side walls, and the cross-section of each transverse bridge along the longitudinal axis of the slit aperture takes a form of a hexagon having two lateral rising edge portions positioned at about the middle of the thickness of the shadow mask.
    Type: Grant
    Filed: May 5, 1975
    Date of Patent: August 10, 1976
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Takeshi Suzuki, Hiroshi Tanaka, Makoto Kudo