Patents by Inventor Makoto Kudo

Makoto Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050086454
    Abstract: The present invention provides a debug function built-in type microcomputer that is capable of restricting outputs only to necessary information to prevent necessary information from being terminated halfway and performing a more accurate tracing in real time, when an output signal line having a bit width fewer than a bit width of an inner bus is used for tracing information on the inner bus. The debug function built-in type microcomputer can be provided with registers that temporarily store bus information prepared for each target bus to be traced, a register writing condition judgment circuit that controls temporary storage of the bus information in the registers according to a trace condition stored in a setting register, and a multiplexer that selects and outputs the bus information temporarily stored in the registers.
    Type: Application
    Filed: March 4, 2003
    Publication date: April 21, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Toshihiko Morigaki, Makoto Kudo
  • Publication number: 20040240307
    Abstract: The invention can provide a device, such as a semiconductor device, that accesses at least one semiconductor storage medium. The semiconductor device can include a given bus master that functions as a bus master, a bus interface that controls access to semiconductor storage media based on access request from the bus master, and a clock-supply-control circuit that controls the presence of the supply of a clock to the bus master based on access state information that indicates a state of access to the semiconductor storage media. The clock-supply-control circuit can stop the supply of the clock to the bus master if the bus interface is at a BUSY state, and supply the clock to the bus master if the bus interface is not at a BUSY state. Accordingly, a power consumption of a semiconductor device that accesses at least one semiconductor storage medium can be reduced.
    Type: Application
    Filed: March 19, 2004
    Publication date: December 2, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Makoto Kudo
  • Publication number: 20040233772
    Abstract: The invention provides a device, such as a semiconductor device, that accesses at least one semiconductor storage medium. The semiconductor device includes a given bus master that functions as a bus master, a bus interface that controls access to semiconductor storage media based on access request from the bus master, and a clock-supply-control circuit that controls the presence of the supply of a clock to the bus interface based on access state information that indicates a state of access to the semiconductor storage media. The clock-supply-control circuit stops the supply of the clock to the bus interface if access is not in execution, and supplies the clock to the bus interface if access is in execution. Accordingly, the power consumption of a semiconductor device that accesses at least one semiconductor storage medium can be reduced.
    Type: Application
    Filed: March 19, 2004
    Publication date: November 25, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Makoto Kudo
  • Patent number: 6799157
    Abstract: An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation mode, the access of CPU to an internal ROM is switched to the access of CPU to the emulation memory through an external bus. The emulation mode is turned ON or OFF through a mode selection terminal or mode selection register. The emulation memory is controlled by a control signal CNT2 different from a control signal CNT1 which controls the external memory. A memory read signal in CNT2 become active at a timing earlier than that of a memory read signal in CNT1. Thus, the instruction is fetched and decoded within one clock cycle. A mode selection terminal is further provided for selecting a mode of performing the boot from the emulation memory, internal ROM or external memory and a made of selecting OPT mode.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: September 28, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Hirofumi Terasawa, Yoshiyuki Miyayama
  • Patent number: 6782032
    Abstract: In a semiconductor laser for emitting light perpendicular to substrate crystal, including, on the substrate crystal, an active layer for generating light, a cavity structure sandwiching the active layer by reflecting mirrors so as to obtain a laser beam from the light generated from the active layer, and a regrown semiconductor layer between the active layer and one of the reflecting mirrors, a regrown interface or a face very close to the regrown interface is formed by a thin film containing dopants of high concentration. With the configuration, an adverse influence of a contamination deposit on the regrown interface is eliminated by delta-doping the regrown interface. The cost is reduced and device resistance is also reduced to 50 &OHgr; or less. Thus, an edge emitting laser (VCSEL) for realizing a optical module achieving a high speed characteristic over 10 Gb/s is obtained.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Kondow, Takeshi Kitatani, Makoto Kudo
  • Publication number: 20040153812
    Abstract: The present invention provides a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer.
    Type: Application
    Filed: November 5, 2003
    Publication date: August 5, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Publication number: 20040153802
    Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.
    Type: Application
    Filed: December 2, 2003
    Publication date: August 5, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makoto Kudo, Yoichi Hijikata
  • Patent number: 6728283
    Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided. The semiconductor laser device has a first semiconductor layer 5 and second semiconductor layers 4, the layer 5 and the layers 4 forming a type-II heterojunction structure, in which an energy of conduction band edge of said first conductor layer 5 is larger than the energy of conduction band of said second semiconductor layers 4. The device has third semiconductor layers 6 as barrier layers formed on both sides of said type-II heterojunction structure.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tomoyoshi Mishima
  • Publication number: 20040070436
    Abstract: A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by ½, ¼, {fraction (2/4)} or ¾ clock period.
    Type: Application
    Filed: October 9, 2003
    Publication date: April 15, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Makoto Kudo, Katsuya Iida
  • Patent number: 6708289
    Abstract: An objective is to provide a microcomputer, electronic equipment and debugging system which can more effectively execute the debugging operation. A mini monitor section (14) can perform data transfer between the mini monitor section and a main monitor section (16). Based on the receive data, the mini monitor section (14) performs debugging processing and also executes a jump command to an address at which an initializing program or a writing program for a flash memory (11) is stored. Receive data (or primitive command) includes GO, write, read, external routine jump commands, and send data contains a flag for announcing an error in data writing. The main monitor section (16) converts a debugging command into a primitive command. Receive data also contains a command identifying data. Both the program debugging and rewriting operations can be performed on a single host system (17) in the present invention.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: March 16, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Makoto Kudo
  • Publication number: 20040039901
    Abstract: A data processing device using pipeline architecture which enables to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a plurality of instruction codes can be fetched, a fetch address operation circuit which calculates a fetch address, a fetch circuit which fetches an instruction code based on the fetch address, and a branch information setting circuit which decodes a branch setting instruction, stores a branch address in a branch address storage register, and stores a branch target address in a branch target address storage register. The fetch address operation circuit compares either a previous fetch address or an expected next fetch address with a value stored in the branch address storage register, and determines a next fetch address to be output, based on the comparison result.
    Type: Application
    Filed: June 20, 2003
    Publication date: February 26, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Makoto Kudo
  • Publication number: 20040039897
    Abstract: A high cost-performance data processing device and electronic equipment are capable of executing an instruction set including a prefix instruction without increasing the circuit scale. The data processing device of the present invention performs pipeline control and includes a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues, a prefix instruction decoder circuit which performs a decode processing only on a prefix instruction, the prefix instruction decoder circuit receiving the instruction code before decoding, judging whether or not the instruction is a given prefix instruction, and causing a target instruction modifying information register to store information necessary for decoding a target instruction when the instruction is the given prefix instruction, and a decoder circuit which receives each of the instruction codes of the instructions other than the prefix instruction as a decode instruction and decodes the decode instruction.
    Type: Application
    Filed: June 20, 2003
    Publication date: February 26, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Makoto Kudo
  • Publication number: 20040015887
    Abstract: The invention provides a simulation method and the like which, where simulations of hardware and software that cooperatively operate with one another are conducted, can readily link software debugging functions to hardware simulation functions. At a first computer, a debugger is used to debut software, and generates commands for simulation of hardware and transmits the same to a second computer. At the second computer, the commands are received at an HDL simulator, and the commands are inputted in a bus interface model included in a hardware simulation model created in an HDL by using the HDL simulator, whereby hardware simulations are performed in cooperation with debugging of software.
    Type: Application
    Filed: March 22, 2002
    Publication date: January 22, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Makoto Kudo
  • Patent number: 6665821
    Abstract: The present invention provides a microcomputer that makes, it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information from within a specified range, and measure execution times, together with electronic equipment and a debugging system comprising this microcomputer. A trace information output section (16) outputs trace information for implementing a real-time trace, to four dedicated terminals. It outputs instruction execution status information (DST[2:0]) of the CPU to three terminals and the PC value (DPCO) of a branch destination when an PC absolute branch has occurred, serially to one terminal. A microcomputer (10) outputs information indicating the start and end of a trace range or execution-time measurement range to DST[2] in a predetermined sequence. A debugging tool (20) determines the start and end of the trace range or execution-time measurement range from the values in DST[2].
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: December 16, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Miyayama, Makoto Kudo, Yoichi Hijikata
  • Patent number: 6658583
    Abstract: A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by 1/2, 1/4, 2/4 or 3/4 clock period.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: December 2, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Makoto Kudo, Katsuya Iida
  • Publication number: 20030191624
    Abstract: The invention provides a debug function built-in type microcomputer that is capable of creating a readily analyzable debug environment and compressing output information, even when an output signal line having a bit width fewer than a bit width of a command bus is used to trace contents on the command bus. In a debug function built-in type microcomputer, a DBG (debug unit) outputs information to be traced, and status information indicative of contents of the information to be traced from a status generation circuit.
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Applicant: Seiko Epson Corporation
    Inventors: Toshihiko Morigaki, Makoto Kudo
  • Publication number: 20030164740
    Abstract: To save power by supplying minimum clocks required for respective blocks. In a clock control system that supplies clocks to a plurality of blocks such as a CPU 4, a bus 5, a peripheral circuit 6 and other circuits 7, a clock supplied from a clock oscillator 1 is supplied to clock control sections 8a, 8b, 8c and 8d that are connected to the blocks 4, 5, 6 and 7, respectively, wherein the clock is converted by the clock control sections 8a, 8b, 8c and 8d into clocks with minimum clock numbers required for operating the blocks 4, 5, 6 and 7, respectively, and supplied to the blocks 4, 5, 6 and 7.
    Type: Application
    Filed: February 25, 2003
    Publication date: September 4, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Makoto Kudo, Keisuke Hashimoto
  • Publication number: 20030103516
    Abstract: In a surface-emitting laser comprising an active region for emitting light and upper and lower DBR's sandwiching this active region from below and above to form resonators, a plurality of selective oxidation layers having an aperture which is an unoxidized region are formed in the upper DBR, lower DBR or both of them and the aperture is made wider stepwise as it becomes farther from the active region, thereby greatly reducing the capacitance of the laser. A high-speed optical module comprising the above surface-emitting laser as a light source has high performance, long service life and is inexpensive.
    Type: Application
    Filed: July 3, 2002
    Publication date: June 5, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Kitatani, Masahiko Kondow, Makoto Kudo, Shinichi Nakatsuka, Masahiro Aoki
  • Patent number: 6570149
    Abstract: There is disclosed a photodetector which is capable of attaining an enhanced detection accuracy, and at the same time permits reduction in the size and manufacturing costs thereof. An avalanche photodiode detects an incident light, in a state of a predetermined bias voltage set thereto. A cooler cools the avalanche photodiode to a predetermined cooling temperature. An amount of an incident signal light incident on the avalanche photodiode is detected based on a detection signal from the avalanche photodiode. A control block adjusts at least one of the bias voltage and the predetermined cooling temperature, thereby holding a value of the detection signal from the avalanche photodiode generated in a state of the incident light being blocked from impinging on the avalanche photodiode, within a predetermined tolerance range.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: May 27, 2003
    Assignee: Hioki Denki Kabushiki Kaisha
    Inventors: Tomoyuki Maruyama, Makoto Kudo, Fumio Narusawa
  • Publication number: 20030086461
    Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided.
    Type: Application
    Filed: November 5, 2002
    Publication date: May 8, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tomoyoshi Mishima