Patents by Inventor Makoto Motoyoshi
Makoto Motoyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343750Abstract: Stacked semiconductor device encompasses an upper semiconductor substrate, an upper insulating film laminated on a principal surface of the upper semiconductor substrate, an upper sealing-pattern orbiting along a periphery of the upper insulating film, a lower chip defining a chip mounting area in at least a part of a principal surface, the principal surface is facing to the upper insulating film, and a lower sealing-pattern disposed on the principal surface of the lower chip, delineating a pattern mating to a topology of the upper sealing-pattern, orbiting around the chip mounting area, configured to implement a metallurgical connector by solid-phase diffusion bonding to the upper sealing-pattern. Hermetical sealed space is established in an inside of the chip mounting area, the upper insulating film and the metallurgical connector.Type: ApplicationFiled: May 14, 2021Publication date: October 26, 2023Inventor: Makoto MOTOYOSHI
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Patent number: 11722800Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: GrantFiled: December 8, 2021Date of Patent: August 8, 2023Assignee: Sony Group CorporationInventors: Shin Iwabuchi, Makoto Motoyoshi
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Publication number: 20220384225Abstract: An alignment-control apparatus encompasses an alignment-assisting tray for aligning a plurality of elements in a batch with highly minute-and-precise configuration, a first transferring unit for collectively transporting the plurality of elements to the alignment-assisting tray, a driving unit for reallocating a convex-ridge of each of the elements toward an concave-ridge assigned to each of the concave cells defined in the alignment-assisting tray, and a second transferring unit for picking up the plurality of elements from the alignment-assisting tray and collectively transporting the plurality of elements.Type: ApplicationFiled: June 24, 2022Publication date: December 1, 2022Inventor: Makoto MOTOYOSHI
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Patent number: 11495565Abstract: A stacked semiconductor device encompasses a mother-substrate, rectangular chips mounted on the mother-substrate, and bump-connecting mechanisms connecting the mother-substrate and the chips by a non-provisional joint-process with a height lower than the height of a provisional joint-process jointing the mother-substrate and the chips. The mother-substrate has unit elements arranged in each of unit-element areas assigned to a first lattice defined on a first main surface of the mother-substrate, the first main surface is divided into chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice. The bump-connecting mechanisms are arranged along a third lattice corresponding to the arrangement of the unit elements, and transmit signals from the unit elements independently to each of the circuits merged in the chips. After the provisional joint-process, the bump-connecting mechanisms can be separated into substrate-side and chip-side connection-elements.Type: GrantFiled: November 6, 2019Date of Patent: November 8, 2022Assignee: Tohoku-Microtec Co., LTD.Inventor: Makoto Motoyoshi
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Patent number: 11462668Abstract: A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor.Type: GrantFiled: November 30, 2020Date of Patent: October 4, 2022Assignee: TOHOKU-MICROTEC CO., LTD.Inventor: Makoto Motoyoshi
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Publication number: 20220124270Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: ApplicationFiled: December 8, 2021Publication date: April 21, 2022Inventors: Shin Iwabuchi, Makoto Motoyoshi
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Patent number: 11228728Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: GrantFiled: April 30, 2020Date of Patent: January 18, 2022Assignee: Sony Group CorporationInventors: Shin Iwabuchi, Makoto Motoyoshi
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Publication number: 20210399184Abstract: A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor.Type: ApplicationFiled: November 30, 2020Publication date: December 23, 2021Applicant: TOHOKU-MICROTEC CO., LTD.Inventor: Makoto MOTOYOSHI
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Publication number: 20210280546Abstract: A stacked semiconductor device encompasses a mother-substrate, rectangular chips mounted on the mother-substrate, and bump-connecting mechanisms connecting the mother-substrate and the chips by a non-provisional joint-process with a height lower than the height of a provisional joint-process jointing the mother-substrate and the chips. The mother-substrate has unit elements arranged in each of unit-element areas assigned to a first lattice defined on a first main surface of the mother-substrate, the first main surface is divided into chip-mounting areas along a second lattice having a smaller number of meshes than the first lattice. The bump-connecting mechanisms are arranged along a third lattice corresponding to the arrangement of the unit elements, and transmit signals from the unit elements independently to each of the circuits merged in the chips. After the provisional joint-process, the bump-connecting mechanisms can be separated into substrate-side and chip-side connection-elements.Type: ApplicationFiled: November 6, 2019Publication date: September 9, 2021Applicant: TOHOKU-MICROTEC CO., LTD.Inventor: Makoto MOTOYOSHI
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Publication number: 20210021776Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: ApplicationFiled: April 30, 2020Publication date: January 21, 2021Inventors: Shin Iwabuchi, Makoto Motoyoshi
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Patent number: 10645324Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: GrantFiled: March 13, 2017Date of Patent: May 5, 2020Assignee: Sony CorporationInventors: Shin Iwabuchi, Makoto Motoyoshi
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Patent number: 10594972Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: GrantFiled: May 9, 2016Date of Patent: March 17, 2020Assignee: Sony CorporationInventors: Shin Iwabuchi, Makoto Motoyoshi
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Patent number: 10468365Abstract: In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel electrodes formed on a signal reading substrate, and wall bump electrodes 34 are further formed on the counter pixel electrodes 33. In order to achieve the above, a resist R is applied, and the resist R is exposed to light to form openings O. When Au sputter deposition is performed on the openings O, only some of the Au is deposited on the bottom surface in the openings O as the counter pixel electrodes 33. The rest of the Au is not deposited on the bottom surface in the openings O, and the most of the remaining Au adheres to the inner walls of the openings O to form wall bump electrodes 34. The bump electrodes 34 are cylindrical, making it possible to reduce the pressure acting on the signal reading substrate by an extent corresponding to the decrease in the bonding area in comparison to conventional bump-shaped bump electrodes.Type: GrantFiled: November 12, 2015Date of Patent: November 5, 2019Assignees: SHIMADZU CORPORATION, TOHOKU-MICROTEC CO., LTD.Inventors: Hiroyuki Kishihara, Toshinori Yoshimuta, Satoshi Tokuda, Yukihisa Wada, Makoto Motoyoshi
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Publication number: 20180331060Abstract: In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel electrodes formed on a signal reading substrate, and wall bump electrodes 34 are further formed on the counter pixel electrodes 33. In order to achieve the above, a resist R is applied, and the resist R is exposed to light to form openings O. When Au sputter deposition is performed on the openings O, only some of the Au is deposited on the bottom surface in the openings O as the counter pixel electrodes 33. The rest of the Au is not deposited on the bottom surface in the openings O, and the most of the remaining Au adheres to the inner walls of the openings O to form wall bump electrodes 34. The bump electrodes 34 are cylindrical, making it possible to reduce the pressure acting on the signal reading substrate by an extent corresponding to the decrease in the bonding area in comparison to conventional bump-shaped bump electrodes.Type: ApplicationFiled: November 12, 2015Publication date: November 15, 2018Inventors: Hiroyuki KISHIHARA, Toshinori YOSHIMUTA, Satoshi TOKUDA, Yukihisa WADA, Makoto MOTOYOSHI
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Patent number: 10129497Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: GrantFiled: November 1, 2017Date of Patent: November 13, 2018Assignee: Sony CorporationInventors: Shin Iwabuchi, Makoto Motoyoshi
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Publication number: 20180315677Abstract: A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.Type: ApplicationFiled: December 21, 2017Publication date: November 1, 2018Applicant: TOHOKU-MICROTEC CO., LTDInventor: Makoto MOTOYOSHI
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Publication number: 20180315727Abstract: A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands. A plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the first lands and each of the second lands. The tubular bumps respectively have major-axis directions to define inclined angles, and are arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps.Type: ApplicationFiled: December 22, 2017Publication date: November 1, 2018Applicant: TOHOKU-MICROTEC CO., LTDInventor: Makoto MOTOYOSHI
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Patent number: 10115649Abstract: A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.Type: GrantFiled: December 21, 2017Date of Patent: October 30, 2018Assignee: TOHOKU-MICROTEC CO., LTD.Inventor: Makoto Motoyoshi
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Patent number: 10115695Abstract: A solid-state imaging device encompasses a detector substrate having a first main-surface, on which a plurality of first lands are arranged in a matrix, and a signal-circuit substrate having a second main-surface, on which plurality of second lands are arranged so as to face the arrangement of the first lands. A plurality of tubular bumps, each of which having a flattened plane pattern, and is provided between each of the first lands and each of the second lands. The tubular bumps respectively have major-axis directions to define inclined angles, and are arranged in the matrix such that the inclined angles differ depending on locations of the plurality of tubular bumps.Type: GrantFiled: December 22, 2017Date of Patent: October 30, 2018Assignee: TOHOKU-MICROTEC CO., LTDInventor: Makoto Motoyoshi
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Patent number: 9955097Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.Type: GrantFiled: February 28, 2014Date of Patent: April 24, 2018Assignee: Sony CorporationInventors: Shin Iwabuchi, Makoto Motoyoshi