Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Abstract: A brain electrode system comprises: a brain electrode body which is placed in the cranium and has an electrode which detects a brain wave signal and a first coil through which an electric current corresponding to the brain wave signal flows; and a communication unit which is disposed on the scalp, has a second coil which magnetically connects with the first coil and in which an induced electromotive force occurs due to a change in the current that flows through the first coil and receives the brain wave signal with the second coil.

Abstract: The present invention provides a CMOS type semiconductor image sensor module in which the aperture ratio of the pixel is improved and at the same time chip use efficiency is attempted to be improved and furthermore, simultaneous shuttering of all the pixels is made possible, and a method of manufacturing the same. The semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip including an image sensor in which a plurality of pixels, each constituted by a photoelectric conversion element and transistors, are arranged, and a second semiconductor chip including an A/D converter array. Preferably, a third semiconductor chip including a memory element array is further laminated. Also, a semiconductor image sensor module of the present invention is constituted by laminating a first semiconductor chip provided with the aforesaid image sensor and a fourth semiconductor chip provided with an analog type nonvolatile memory array.

Abstract: A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: A brain probe includes: a core probe made from a metal; and n electrode plates attached so as to cover an entire side surface circumference of the core probe and forming n side planes providing an n-angular cross section (n is an integer equal to or greater than 3). Each of the electrode plates is manufactured by a LSI manufacturing process, and provided with at least one electrode and a lead-out wiring extending in a longitudinal direction of a side plane from each of the at least one electrode.

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: A high-capacity magnetic memory device in which the magnetic field for writing is nearly uniform for all memory elements. It is realized by reducing the deformation of resist pattern which occurs in photolithography when mask patterns are close to each other. The magnetic memory device is an MRAM composed of a large number of memory cells, each including one TMR element, one transistor for reading (selection), and reading plugs that connect the TMR element to the transistor for reading (selection). These memory cells are arranged such that the TMR elements are in a pattern of translational symmetry. For writing, memory cells are connected by the bit lines and the writing word lines which intersect orthogonally. The long axis of the TMR element is oriented aslant 45° with respect to these lines, so that the TMR elements are capable of toggle-mode writing.

Abstract: A magnetic memory device exhibits improved writing characteristics by providing a magnetic flux concentrator which efficiently applies the magnetic field, which is generated by the writing word line, to the memory layer of the TMR element. The magnetic memory device (1) is composed of the TMR element (13), the writing word line (the first wiring) (11) which is electrically insulated from the TMR element (13), and the bit line (the second wiring) (12) which is electrically connected to the TMR element (13) and intersecting three-dimensionally with the writing word line (11), with the TMR element (13) interposed therebetween. The magnetic memory device (1) is characterized as follows. The magnetic flux concentrator (51) of high-permeability layer is formed along at least the lateral sides of the writing word line (11) and the side of the writing word line (11) which is opposite to the side facing the TMR element (13).

Abstract: A non-volatile magnetic memory device is proposed, which provides sufficient magnetic shielding performance for external magnetic fields. A first magnetic shield layer 60a and a second magnetic shield layer 60b, both made of a soft magnetic metal, are formed respectively on the bottom surface of the transistor section 20, which is the mounting side of the MRAM device 10, and on the top surface of the bit line 50, which is opposite to the bottom surface of the mounting side of the MRAM device 10. On the second magnetic shield layer 60a, a passivation film 70 is formed. The magnetic flux penetrated from the external magnetic field, is suppressed below the inversion strength of the MRAM device 10, thereby improving reliability.

Abstract: A magnetic memory device in which the memory cell of MRAM is reduced in size, and a method for producing the magnetic memory device are provided. The lower wiring is formed below the word line. The connecting hole and the plug connected to it are provided. The reading wiring and the lower layer wiring are connected through this plug. Alternatively, the local wiring is provided in the connecting hole and the reading wiring and the lower layer wiring are connected. In this way it is possible to form the connecting hole close to the word line, and hence it is possible to reduce the cell size in the direction along the bit line.

Abstract: A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, control signals are output from the circuit selection switching elements. As the connection elements, preferably use is made of magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. As the circuit elements, use can be made of magnetoresistance effect elements or resistance control elements.

Abstract: An TMR-type MRAM comprising a transistor for selection; a first connecting hole; a first wiring (write-in word line); a second insulating interlayer covering a first insulating interlayer and the first wiring; a TRM device formed on the second insulating interlayer; a second wiring (bit line) formed on a third insulating interlayer; and a second connecting hole formed through the second insulating interlayer and connected to the first connecting hole, in which an end face of an extending portion of the other end of the TRM device is in contact with the second connecting hole.

Abstract: A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, and control signals are output from the circuit selection switching elements. The connection elements may be magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. The circuit elements may also be magnetoresistance effect elements or resistance control elements.

Abstract: A semiconductor integrated circuit device able to configure a desired circuit in accordance with a circuit configuration instruction signal given from the outside and able to operate the configured circuit is provided. The semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, control signals are output from the circuit selection switching elements, and the desired circuit is configured by combining the circuit elements via said connection elements which become the conductive state or the nonconductive state in accordance with the control signals.

Abstract: A magnetic memory device in which the memory cell of MRAM is reduced in size, and a method for producing the magnetic memory device are provided. The lower wiring is formed below the word line. The connecting hole and the plug connected to it are provided. The reading wiring and the lower layer wiring are connected through this plug. Alternatively, the local wiring is provided in the connecting hole and the reading wiring and the lower layer wiring are connected. In this way it is possible to form the connecting hole close to the word line, and hence it is possible to reduce the cell size in the direction along the bit line.