Abstract: A method for vehicle design includes accessing a plurality of confidential documents secured by at least one access mechanism. The method also includes extracting a set of parallel data including at least one of: a vehicle feature implementing the innovative vehicle technology, a vehicle feature cost, and a vehicle feature production time, and storing each set of parallel data in a parallel data store. The method includes mapping a customer vehicle attribute to the vehicle feature in each set of parallel data by applying a customer core values model. Further, the method includes identifying potential vehicle features from the parallel data store that satisfy one or more production constraints and optimizes customer value according to the customer vehicle attributes. The method also includes generating a vehicle feature production list for the new vehicle model based on the potential vehicle features.

Abstract: According to one embodiment, a disk device includes a disk, a head that performs data read/write processing on a recording region of the disk, a controller that performs a media scan processing for detecting the presence or absence of a defect in a sector in the recording region of the disk in track unit. When the controller performs the media scan processing on a first sector and a second sector arranged in the track, and a third sector arranged between the first sector and the second sector, the controller performs skip processing in which the controller scans the first sector and the second sector, and does not scan the third sector.

Abstract: According to one embodiment, a disk device includes a disk, a head that performs data read/write processing on a recording region of the disk, a controller that performs a media scan processing for detecting the presence or absence of a defect in a sector in the recording region of the disk in track unit. When the controller performs the media scan processing on a first sector and a second sector arranged in the track, and a third sector arranged between the first sector and the second sector, the controller performs skip processing in which the controller scans the first sector and the second sector, and does not scan the third sector.

Abstract: A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

Abstract: A semiconductor device includes a package substrate having a chip mounting surface with at least a plurality of first substrate-side pads and a plurality of second substrate-side pads, a rectangular first semiconductor chip having a first main surface fixed on the chip mounting surface, a plurality of first bonding wires through which a plurality of first pads arranged along one side of a second main surface of the first semiconductor chip and the first substrate-side pads are bonded to each other, a rectangular second semiconductor chip having a third main surface fixed on the second main surface, and a plurality of second bonding wires through which a plurality of second pads arranged along one side of a fourth main surface of the second semiconductor chip and the second substrate-side pads are bonded to each other.

Abstract: A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

Abstract: A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

Abstract: A valve train for an internal combustion engine including a plurality of cylinders having different valve mechanism constructions, in which the valve train has a correcting member for correcting a difference in valve lift amount that is produced between the plurality of cylinders due to a difference in construction between valve mechanisms so as to make valve lift amounts of the plurality of cylinders substantially uniform.

Abstract: A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the cylinders is operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. Operating parameters of a vehicle driven by the engine is detected. The all-cylinder operation or the partial-cylinder operation is performed according to the detected operating parameters. An oxygen concentration sensor is provided in an exhaust system corresponding to the at least one cylinder which is halted during the partial-cylinder operation. A failure of the oxygen concentration sensor is diagnosed in a predetermined operating condition including a fuel-cut operation of the engine upon deceleration. The partial-cylinder operation is permitted after completion of the failure diagnosis.

Abstract: A valve train for an internal combustion engine including a plurality of cylinders having different valve mechanism constructions, characterized in that the valve train has correcting member for correcting a difference in valve lift amount that is produced between the plurality of cylinders due to a difference in construction between valve mechanisms so as to make valve lift amounts of the plurality of cylinders substantially uniform.

Abstract: A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the cylinders is operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. Operating parameters of a vehicle driven by the engine is detected. The all-cylinder operation or the partial-cylinder operation is performed according to the detected operating parameters. An oxygen concentration sensor is provided in an exhaust system corresponding to the at least one cylinder which is halted during the partial-cylinder operation. A failure of the oxygen concentration sensor is diagnosed in a predetermined operating condition including a fuel-cut operation of the engine upon deceleration. The partial-cylinder operation is permitted after completion of the failure diagnosis.

Abstract: A control system for an internal combustion engine having a plurality of cylinders and a switching mechanism for switching between an all-cylinder operation in which all of the plurality of cylinders are operated and a partial-cylinder operation in which at least one of the plurality of cylinders is halted. A condition for performing the partial-cylinder operation is determined, based on the detected operating parameters of the vehicle driven by the engine. A result of the determination is modified so that the partial-cylinder operation may be continued, when the detected operating parameters satisfy a predetermined continuation condition within a predetermined time period from the time a vehicle operating state where the condition for performing the partial-cylinder operation is satisfied, has changed to another vehicle operating state where the condition for performing the partial-cylinder operation is not satisfied.

Abstract: An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device.

Abstract: A semiconductor device has an internal circuit (2), a PAD, a NMOS Tr (QN) as a protective transistor formed between a node (N) on a signal line and a first power source (Vss), and a NOR gate (G1) as a logical gate connected to a gate as a control terminal of the NMOS transistor (QN). The internal circuit (2) is connected to the PAD through the signal line. The NOR gate (G1) keeps the protective transistor (QN) an OFF state during a normal operation of the internal circuit (2). In addition, the semiconductor device further includes a test circuit (21). The output from the NOR gate (G1), whose one input is the output from the test circuit (21), is supplied to the gate of the NMOS transistor (QN). The output from the test circuit (21) is thereby output to outside through the NMOS transistor (QN) and the PAD.

Abstract: There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n−1)-th (n≧1) output selection control circuits; first through (2n−1)-th output transistor circuits which are provided so as to correspond to the first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n−2)-th output signal lines, each of the first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . .

Abstract: There is provided a semiconductor memory device capable of preventing the deterioration of access characteristics between output signal lines. The semiconductor memory device comprises: first and second cell arrays, each of which has the same number of memory cells; first through (2n−1)-th (n≧1) output selection control circuits; first through (2n−1)-th output transistor circuits which are provided so as to correspond to the first through (2n−1)-th output selection control circuits, and each of which receives the output of a corresponding one of the output transistor circuits; and first through (4n−2)-th output signal lines, each of the first and second cell arrays being divided into k (k≧2) first through k-th section parts, each of which has 2n−1 first through (2n−1)-th output parts and at least one auxiliary input/output part, the i-th (i=1, . . .

Abstract: The gates 31, 32, 33 and 34 of a pair of driver transistors Q1, Q2 and a pair of address-selecting transistors Q3, Q4 are arranged so as to be perpendicular to bit lines BL, /BL. The drain regions of the driver transistors Q1, Q2 forming a flip-flop are arranged point-symmetrically around an element isolating region. The source regions of the driver transistors Q1, Q2 are arranged point-symmetrically. Similarly, the address-selecting transistors Q3, Q4 are arranged point-symmetrically. An upper wiring layer connected to two gates of the transistors are arranged so as to be perpendicular to the bit lines BL, /BL. Two Vss lines are formed in the same layer as that for the bit lines BL, /BL and arranged on both sides of the bit lines BL, /BL in parallel thereto. The Vss lines are connected to the source regions of the driver transistors.

Abstract: A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.

Abstract: A semiconductor device is provided with at least one transistor formed on a semiconductor substrate, the transistor being provided with a conductive sidewall spacer, and at least one conductive film formed so as to face a gate of the transistor via an insulative film, the conductive film covering at least an entire region of a gate region of the transistor and acting as a capacitor electrode. The conductive sidewall spacer and the conductive film are connected together. A potential is supplied to the conductive sidewall spacer and the conductive film, the potential being different from a potential of the gate of the transistor.

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition.