Abstract: A drive circuit which includes a plurality of load MOS transistors coupled in series between a positive power source terminal and a node point, a plurality of drive MOS transistors coupled in parallel between a ground terminal and the node point, a static type bootstrap buffer circuit connected at the input terminal to the node point, and a gate control circuit for controlling the conduction states of the load and drive MOS transistors. The gate control circuit renders the load MOS transistors conductive, and then renders the drive MOS transistors nonconductive after the load MOS transistors are rendered fully conductive.

Abstract: A semiconductor device having multiple conductive layers which are satisfactorily connected to one another is disclosed. The multiple conductive layers are respectively insulated by insulation layers and are formed on the semiconductor substrate where circuit elements are formed. Each multiple conductive layer is connected through contact holes having the same depth and at least one conductive layer is connected to the first conductive layer thereunder through an additional conductive layer formed at the same time that the second conductive layer is formed.

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above the drain of the first insulation gate FET transistor, and the second polycrystalline silicon layer is provided above the drain of the second insulation gate FET transistor.

Abstract: The region constituting the rectify-charge pump circuit of a self substrate bias circuit is surrounded by a capacitive region, and the fluctuated minority carriers induced in this region are absorbed.

Abstract: A memory device of the invention has a P type substrate, a first drain area of N type formed in the substrate, a second drain area of N type formed in the substrate close to the first drain area, and a source area of N.sup.+ type formed around the first and second drain areas so that the source area continuously surrounds the drain areas from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas and the surrounding arrangement of the source area decreases minority carriers generated around the drain areas and prevents unbalanced carrier absorption of the drain areas, thereby suppressing the occurrence of a soft error.

Abstract: An address buffer circuit is provided which has first and second MOS transistors whose current paths are connected in series with each other and whose gates are supplied with input signals of opposite phases, and third and fourth MOS transistors whose current paths are connected in series with each other. The first and third MOS transistors are of I-type. The gate of the third MOS transistor is connected to a junction of the first and second MOS transistors and the gates of the second and fourth MOS transistors are commonly connected. The address buffer circuit further has a MOS transistor which controls the conduction state of the third MOS transistor in response to an external control signal.

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

Abstract: A semiconductor integrated circuit having a memory and an adjacent peripheral circuit generating minority carriers which can destroy data in a portion of the memory at low temperatures. The load resistance in the portion is made lower or the storage capacity is made higher in the portion than in the remainder of the memory so that at low temperatures data is not lost and the energy consumption of the circuit is not unduly increased.

Abstract: An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.