Abstract: A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit.

Abstract: A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition.

Abstract: A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

Abstract: A semiconductor memory device includes an address input circuit for receiving an address signal and outputting an internal address signal corresponding to the received address signal; an address decoder for decoding the internal address signal and outputting a decoded signal; a memory cell array having a plurality of memory cells each capable of storing data, as selected by the decoded signal, the selected memory cell outputting memory cell data; and an output circuit for outputting a truth data and false data at the same time in accordance with the output memory cell data of the selected memory cell.

Abstract: A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.

Abstract: In the semiconductor memory device, memory cells are divided into plural blocks; each block is further divided into plural I/O unit groups; and furthermore each I/O unit group is divided into plural small groups. The word lines provided for each small group of memory cells arranged at similar locations in each unit group are connected in common to a word line selecting line selected by a select circuit. Therefore, the number of memory cells connected to one word line can be reduced to decrease the power consumption and to increase the operating speed, without increasing the wiring capacitance and the chip size.

Abstract: A semiconductor memory device having an internal circuit which is powered from a first power source terminal and outputs an output drive signal corresponding to a stored data in a selected memory cell of a memory cell array; and output buffer unit which is powered from a second power source terminal and operates in such a manner that a gate is closed or opened in accordance with whether the output drive signal is low level or high level, and an output signal of low level or high level corresponding to closed gate or opened gate is outputted via an external output terminal to the external; and a level change suppressing circuit for suppressing a level change of the output drive signal as viewed from the output buffer, by connecting the output terminal of the internal circuit to one of the second power source terminal and the external output terminal, when the potential at the second power source terminal changes relatively with respect to the potential at the first power source terminal as the output signal at

Abstract: A memory cell array includes static memory cells arranged in an array of n rows.times.m columns. Each of the memory cells includes MOS transistors formed in a semicondutor substrate and in a corresponding one of well regions of the conductivity type opposite to that of the semiconductor substrate. The well regions are independently formed for each row or for every two or more rows of the memory cell array. The well regions are connected to the respective sources of MOS transistors formed in the well regions. The source and backgate of each of the MOS transistors formed in the well regions are connected to the common source wirings for each of the independently formed well regions. Isolation circuits are respectively connected between the common source wirings for the repective well regions and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.

Abstract: A semiconductor IC device including a main circuit block and at least one subcircuit block, each having a ground terminal, a supply voltage terminal and an input or output terminal. A first ground line is connected to the ground terminal of the main circuit block and arranged within a wiring domain of the main circuit block and adjacent to the subcircuit blocks. A second ground line is connected to the ground terminal of the subcircuit block and arranged within a wiring domain of the subcircuit block and adjacent to the main circuit block. Protective elements are connected between the first and second ground lines so as to form short circuits through at least one of the first and second ground lines.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells, each of the cells being capable of storing a data and being selected by an address; a pair of data lines to which a pair of complementary data from a selected memory cell are imputted; an equalizer for short-circuiting and equalizing the pair of data lines when an equalizing signal is applied; an output circuit for outputting a single signal corresponding to the pair of complementary data from the pair of data lines; a pair of latch circuits provided between the output circuit and the equalizer for the pair of data lines, the pair of latch circuits holding the pair of complementary data; a pair of output buffer circuit provided between the pair of latch circuits and the equalizer for the pair of data lines, the pair of output buffer circuits capable of taking a low impedance state wherein the potentials per se of the pair of data lines are outputted, and a high impedance state wherein the potential change of the pai

Abstract: In a static random access memory, when data is written into said plurality of memory cells, a write enable signal is set at a low level, and after the data write is completed, the write enable signal is set at a high level. In response to a level change of the write enable signal from a low level to a high level, a pulse generator generates a pulse signal in "1" level and with a given pulse width. In response to this pulse signal, a first MOS transistor is turned on to short paired bit lines. This pulse signal turns on second and third MOS transistors. Then, the potentials on the paired bit lines are pulled up to a power source potential. As a result, of the two bit lines, the bit line which has been set at a low potential immediately after data is written, is charged. A pulse extension/inverting circuit extends the pulse width of the pulse signal generated by a pulse generator by a given time period, and inverts a logical state of the pulse signal.

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

Abstract: This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Abstract: An integrated circuit includes an input buffer circuit and an output buffer circuit. The source voltage to the input buffer circuit and the output buffer circuit are supplied through bonding pads formed independently on a semiconductor chip, and electrically connected to a source potential lead pin. The input node of the input buffer circuit is coupled to the source potential of the output buffer circuit with a capacitor.

Abstract: A random access memory comprises a semiconductor body of one conductivity type, at least one first well region of an opposite conductivity type formed in the surface area of the semiconductor body, and a memory cell array having a plurality of memory cells formed in the first well region. A peripheral circuit for driving the memory cell array is formed in at least one second well region of the opposite conductivity type formed separately from the first well region in the surface area of the semiconductor body. The second well region is set at a bias level deeper than the first well region.

Abstract: A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

Abstract: A semiconductor device having a pair of wiring layers connected in parallel with each other in which a first wiring layer is formed over a semiconductor substrate through a insulation layer. The first wiring layer is made of poly-Si and has relatively high resistivity. Therefore a second wiring layer is formed over the first wiring layer through an insulation layer. A portion of the second wiring layer has low conductivity and is parallel connected to the first wiring layer in order to reduce the resistivity of the wiring layer. Another portion of the second wiring layer has low conductivity and is used as resistive means.

Abstract: A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders provided for each row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits provided for each of the memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.

Abstract: An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit. The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the gate-protective circuit is constructed by a MOSFET which is connected between a power supply and the D type MOSFET and whose gate is connected to the power supply. The gate of the D type MOSFET is protected by the gate-protection circuit even if noise exists on the power supply line.

Abstract: A semiconductor circuit has a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the gate connected to receive an inverted form of the input signal after a delay time and having the current path connected between the node and a reference potential terminal and a capacitor connected between the gate of the first MOS transistor and the node. The semiconductor circuit also has a short pulse generator.