Patents by Inventor Makoto Shibuya

Makoto Shibuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11656021
    Abstract: A refrigerator having detachably adjacent cabinets is provided. The refrigerator includes a connection mechanism interposed between cabinets adjacent to each other and connecting the cabinets to each other and a manipulation portion configured to drive the connection mechanism by being manipulated from outside, wherein the connection mechanism is configured for the cabinet on one side is pulled toward the cabinet on the other side by a manipulation of the manipulation portion.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 23, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Makoto Shibuya, Kentaro Kan, Manabu Kikuchi, Tomohiko Matsuno
  • Publication number: 20230133029
    Abstract: A semiconductor package includes a leadframe including a plurality of pre-separated leads on at least opposing sides. There is metal plating on a distal end of the plurality of pre-separated leads including on an outer facing edge. A semiconductor die having bond pads is mounted on the leadframe having the bond pads electrically connected to the plurality of pre-separated leads.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Applicant: Texas Instruments Incorporated
    Inventor: Makoto Shibuya
  • Publication number: 20230137762
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Publication number: 20230095630
    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Makoto SHIBUYA, Masamitsu MATSUURA, Kengo AOYA
  • Patent number: 11601065
    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
  • Publication number: 20230060830
    Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Makoto Shibuya, Kengo Aoya
  • Publication number: 20230038411
    Abstract: A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.
    Type: Application
    Filed: August 3, 2021
    Publication date: February 9, 2023
    Applicant: Texas Instruments Incorporated
    Inventor: Makoto Shibuya
  • Patent number: 11574855
    Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: February 7, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Noboru Nakanishi
  • Publication number: 20230005880
    Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 5, 2023
    Inventors: Anindya Poddar, Ashok Surendra Prabhu, Hau Nguyen, Kurt Edward Sincerbox, Makoto Shibuya
  • Publication number: 20220352055
    Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 3, 2022
    Inventors: Makoto SHIBUYA, Makoto YOSHINO, Kengo AOYA
  • Publication number: 20220230952
    Abstract: In described examples, a packaged semiconductor device includes a frame, a pre-fabricated interposer, and an integrated circuit die. The frame includes multiple conductive frame leads and multiple conductive connection points, as well as a hole in the frame surrounded by the frame leads and the conductive connection points. The pre-molded interposer has an external perimeter including multiple conductive interposer leads, and is for insertion into the hole. At least one of the interposer leads does not extend to the external perimeter of the interposer. The die is electrically coupled to selected ones of the frame leads and of the interposer leads. The interposer is inserted into the hole and coupled to the frame, and the frame, interposer, and die are together encapsulated by encapsulation material.
    Type: Application
    Filed: January 4, 2022
    Publication date: July 21, 2022
    Inventor: Makoto Shibuya
  • Patent number: 11387179
    Abstract: An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Kengo Aoya, Woochan Kim, Vivek Kishorechand Arora
  • Publication number: 20220208660
    Abstract: An electronic package includes an electronic component including terminals, a plurality of surface contacts, at least some of the surface contacts being electrically coupled to the terminals within the electronic package, a mold compound covering the electronic component and partially covering the surface contacts with a bottom surface exposed from the mold compound, and a plurality of wires extending from exposed surfaces of the surface contacts, each of the wires providing a solderable surface for mounting the electronic package at a standoff on an external board.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Makoto Shibuya, Ayumu Kuroda, Kengo Aoya
  • Publication number: 20220090844
    Abstract: A refrigerator having detachably adjacent cabinets is provided. The refrigerator includes a connection mechanism interposed between cabinets adjacent to each other and connecting the cabinets to each other and a manipulation portion configured to drive the connection mechanism by being manipulated from outside, wherein the connection mechanism is configured for the cabinet on one side is pulled toward the cabinet on the other side by a manipulation of the manipulation portion.
    Type: Application
    Filed: September 8, 2021
    Publication date: March 24, 2022
    Inventors: Makoto SHIBUYA, Kentaro KAN, Manabu KIKUCHI, Tomohiko MATSUNO
  • Publication number: 20220049891
    Abstract: A refrigerator is provided. The refrigerator includes a main cabinet including a cooling device to generate cold air, a sub-cabinet detachably connected to the main cabinet, a cold air relay duct provided to connect the main cabinet and the sub-cabinet and having a cold air flow path to allow the cold air generated by the cooling device to be delivered to the sub-cabinet, and a heat blocking member provided in a portion of the cold air flow path at which the main cabinet and the cold air relay duct are connected and in a portion of the cold air flow path at which the sub-cabinet and the cold air relay duct are connected.
    Type: Application
    Filed: July 26, 2021
    Publication date: February 17, 2022
    Inventors: Kentaro KAN, Hiroshi NAKAMURA, Makoto SHIBUYA, Manabu KIKUCHI, Ryota AOKI, Tomohiko MATSUNO
  • Patent number: 11217513
    Abstract: An integrated circuit (IC) package includes an encapsulation package that contains an integrated circuit die attached to a lead frame. A set of contacts is formed on the package that each have an exposed contact sidewall surface and an exposed contact lower surface. A protective layer of solder wettable material covers each contact sidewall surface.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daiki Komatsu, Makoto Shibuya
  • Patent number: 11217522
    Abstract: In described examples, a packaged semiconductor device includes a frame, a pre-fabricated interposer, and an integrated circuit die. The frame includes multiple conductive frame leads and multiple conductive connection points, as well as a hole in the frame surrounded by the frame leads and the conductive connection points. The pre-molded interposer has an external perimeter including multiple conductive interposer leads, and is for insertion into the hole. At least one of the interposer leads does not extend to the external perimeter of the interposer. The die is electrically coupled to selected ones of the frame leads and of the interposer leads. The interposer is inserted into the hole and coupled to the frame, and the frame, interposer, and die are together encapsulated by encapsulation material.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 4, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Makoto Shibuya
  • Publication number: 20210375730
    Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.
    Type: Application
    Filed: August 10, 2021
    Publication date: December 2, 2021
    Inventors: Makoto Shibuya, Noboru Nakanishi
  • Publication number: 20210265214
    Abstract: In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Inventor: Makoto Shibuya
  • Patent number: 11088055
    Abstract: A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Noboru Nakanishi