Abstract: The use of a Nitride layer or a silicon-nodule layer capable of location-specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Buckyball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Buckyball Oxide layer is used as the storage element. The problem of location-specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.

Abstract: The use of a Nitride layer or a silicon-nodule layer capable of location-specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Bucky-ball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Bucky-ball Oxide layer is used as the storage element. The problem of location-specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.

Abstract: Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

Abstract: PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between external systems, such that the scalability can be applied to enable data transport between connected systems to form a cluster of systems is proposed. These connected systems can be any computing or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

Abstract: A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The method further involves recognizing that an output queue has room to receive information and that an intermediate queue that provides information to the output queue does not have information waiting to be forwarded to the output queue. The method also involves generating a second request to read information from the input RAM so that at least a portion of the room can be filled. The method also involves granting one of the first and second requests.

Abstract: Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

Abstract: Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

Abstract: The use of a Nitride layer or a silicon-nodule layer capable of Location-Specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Buckyball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Buckyball Oxide layer is used as the storage element. The problem of Location-Specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.

Abstract: In the past the high voltage needs and cell leakage currents have limited the scalability of the Nitride cell and made the poly silicon floating gate cell the primary contender for Non-Volatile memories. As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon floating gate cell has approached its scaling limitations. This has re-kindled the interest in the nitride cell. In order to scale the nitride cell it is necessary to remove the high voltage requirements that limit scaling of the memory junctions and isolation and the high inherent leakage of unselected cells due to over erase of the cells. It is well known that the nitride area where the storage happens is only of the order of 300 Angstroms close to the junctions used for generating the energetic carriers by impact ionization (Channel Hot Electron Programming). The charges once stored do not move around by conduction in Nitride and hence can be considered stationary.

Abstract: Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Abstract: This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

Abstract: Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area.

Abstract: A Channel Accelerated Carrier Tunneling method of programming high speed, low voltage, memory cells, typically non-volatile memory cells, using the majority carriers available in an MOS channel is disclosed. The method uses the velocity of the majority carriers in the channel, the kinetic energy available, to enhance the accelerating voltage applied towards a storage electrode to enhance the collection and storage of the carriers by the storage electrode, typically a floating gate in a non-volatile memory. The method envisages a discontinuity in the channel which allows the carriers to be accelerated towards it. By having a storage electrode with voltage gradient, over lying the discontinuity, in the direction of acceleration of the carriers, these carriers can be made to pass through the oxide barrier of the gate and accumulate on the storage node.

Abstract: This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

Abstract: A structure for low voltage, high density, non-volatile memory cell, with ability to write electrically using the CACT or Channel Accelerated Carrier Tunneling method for programming memories and erase electrically by tunneling, having separate regions for write and erase for high reliability, is described. These cells have the ability to write by transferring charge to the storage gate using the majority carriers in the channel of the MOS transistor, eliminating the need for generation of high fields needed for the hot electron EPROM write method used in the prior art flash memories. In addition the use of the carrier velocity to enhance the write process reduce the need for the high write -voltages on the gates as compared to the present EEPROM and EPROM write memories.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.