Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern.

Abstract: A photolabile compound, an oligomer probe array, and a substrate for oligomer probe array comprising the same, and a manufacturing method of the same are disclosed.

Abstract: Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.

Abstract: A microarray, a substrate for a microarray and more productive methods of fabricating the microarray and the substrate are provided. The microarray includes a substrate divided into a first region and a second region; a plurality of linkers represented by formula 1 or 2: wherein X is a site coupled to the substrate, R is a hydroxyl, aldehyde, carboxyl, amino, amide, thiol, halo, epoxy, or sulfonate group, m is an integer in the range of 3 to 16, p is an integer in the range of 1 to 30, and q is an integer in the range of 1 to 15, directly coupled to the substrate in the first region but not coupled to the substrate in the second region; and a plurality of probes coupled to the respective linkers.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A non-linear silicon compound is provided. The non-linear silicon compound may be a non-linear aromatic compound used as a linker for manufacturing an oligomer probe array. The non-linear silicon compound may reduce self-aggregation so as to form a stable and uniform monolayer. As a result, upon hybridization analysis, the fluorescent intensity may be increased.

Abstract: A polymer, a top coating layer, a top coating composition and an immersion lithography process using the same are disclosed. The top coating layer polymer may include a deuterated carboxyl group having a desired acidity such that the top coating layer polymer may be insoluble with water and a photoresist, and soluble in a developer. The polymer may be included in a top coating layer and a top coating composition.

Abstract: First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively.

Abstract: Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.

Abstract: Provided is a substrate for an oligomer probe array to which a photolabile material having an acetylene derivative is directly attached or attached via a linker.

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: A microarray, a substrate for a microarray and more productive methods of fabricating the microarray and the substrate are provided. The microarray includes a substrate divided into a first region and a second region; a plurality of linkers represented by formula 1 or 2: wherein X is a site coupled to the substrate, R is a hydroxyl, aldehyde, carboxyl, amino, amide, thiol, halo, epoxy, or sulfonate group, m is an integer in the range of 3 to 16, p is an integer in the range of 1 to 30, and q is an integer in the range of 1 to 15, directly coupled to the substrate in the first region but not coupled to the substrate in the second region; and a plurality of probes coupled to the respective linkers.