Abstract: A method for manufacturing a semiconductor device comprises: forming an N region and P region on a substrate, forming wiring so as to connect one or both of these N and P regions; and performing a processing step on a semiconductor substrate on which the upper surface of said wiring is exposed using a liquid, wherein said processing step is performed in a state in which the wavelength of light radiated onto said semiconductor substrate is 500 nm to less than 1 ?m, so that problems such as wiring connection defects for which there is the risk of occurring in the cleaning step are prevented by performing the cleaning step during, before or after a step that includes chemical mechanical polishing (CMP) for forming the above wiring.

Abstract: A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.

Abstract: A semiconductor device having a structure which can be manufactured with a higher yield includes a local interconnection layer 14 (a first interconnection layer) on a semiconductor substrate 10 and a global interconnection layer 18 (a second interconnection layer) on the local interconnection layer 14. The local interconnection layer 14 and the global interconnection layer 18 include a local interconnection 24 (a first interconnection) and a global interconnection 28 (a second interconnection), respectively, and the global interconnection 28 is thicker than the local interconnection 24. The local interconnection layer 14 and the global interconnection layer 18 also have a dummy interconnection 34 (a first dummy interconnection) and a dummy interconnection 38 (a second dummy interconnection), respectively. The dummy interconnection 34 is narrower than the dummy interconnection 38.

Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.

Abstract: In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Abstract: A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched between the first guard ring and the second guard ring is divided by the first connections into a plurality of subareas. Even if the first guard ring is partly defective, water enters from outside into only the subarea which is contiguous to the defective part of the first guard ring.

Abstract: A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.

Abstract: A semiconductor device is provided which is capable of preventing corrosion of circuit portion and ensuring high reliability by optimizing a construction of outer-surrounding protecting walls that surround an internal element region to completely stop invasion of water from an edge portion of a semiconductor chip. The outer-surrounding protecting walls made up of a wiring layer and a via layer are formed in a manner to surround the internal element region and that a distance between an edge portion of the semiconductor chip and the outermost-surrounding protecting wall is 30 &mgr;m. The outer-surrounding protecting wall is so formed as to doubly or more surround the internal element region.

Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Abstract: In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Abstract: A semiconductor apparatus includes an under layer, a first insulating layer and a first conductive portion. The under layer is formed above a substrate. The first insulating layer is formed on the under layer. The first conductive portion is formed in a first concave portion which passes through the first insulating layer to the under layer. The first conductive portion includes a first barrier metal layer and a first metal portion. The first barrier metal layer is formed on a side wall and a bottom surface of the first concave portion. The first metal portion is formed on the first barrier metal layer such that the rest of the first concave portion is filled with the first metal portion. The first metal portion includes a first alloy including copper and aluminium.

Abstract: A semiconductor device having a plurality of interconnection layers includes signal lines formed of copper according to a single damascene process, vias formed of tungsten beneath the signal lines according to a single damascene process, and power and ground lines and vias therebeneath formed of copper according to a dual damascene process. Since copper has a better heat radiating capability than tungsten, the vias in all the layers have a better heat radiating capability than those formed of tungsten.

Abstract: An insulating layer is formed on a whole surface of a wafer. Recesses such as wiring grooves are formed in the insulating layer. A part of the insulating layer is removed on a region whose distance from the peripheral edge of the wafer is a value x or less. After a conductive film is formed on the whole wafer surface, a part is removed on a region whose distance from the peripheral wafer edge is a value y (y<x) or less. Chemical mechanical polishing removes a part of the conductive except in the recesses. Thereafter, wet etching removes part of the conductive film on a region from the peripheral wafer edge of z (x<z) or less. An interlayer insulating film is formed on the whole wafer surface.

Abstract: A silicon oxide film, a silicon oxynitride film, and a silicon oxide film are formed on a semiconductor substrate. A silicon nitride film and a silicon oxide film are formed, and, using an overlying resist film as a mask, are subjected to dry etching to form via-holes. Oxygen plasma ashing and resist removal are carried out. The silicon nitride film is subjected to dry etching to expose the surface of the copper film and the resist residue is removed. A tungsten film is then formed to bury the via-holes with tungsten. Excess tungsten film is removed by CMP and rinsing, thereby forming via-plugs that are composed of the tungsten film that remains in the via-holes. Silicon oxide film is formed over this structure. Using a resist film as a mask, wiring trenches are formed in the silicon oxide film. The resist film and etching residue are then removed. Amine removing solution that has entered seams in the tungsten film is vaporized by a heat treatment.

Abstract: A method for forming a multilayer interconnection structure on a wafer by using a damascene technique includes the steps of separating the area of the wafer into a peripheral area, an intermediate area and a central area as viewed from the outer periphery toward the center of the wafer. The lower-level interconnections having a smaller width are formed in the intermediate and central areas, whereas the upper-level interconnections having a larger width are formed in the central area.

Abstract: An insulating layer is formed on a whole surface of a wafer. Recesses such as wiring grooves are formed in the insulating layer. A part of the insulating layer is removed on a region whose distance from the peripheral edge of the wafer is a value x or less. After a conductive film is formed on the whole wafer surface, a part is removed on a region whose distance from the peripheral wafer edge is a value y (y<x) or less. Chemical mechanical polishing removes a part of the conductive except in the recesses. Thereafter, wet etching removes part of the conductive film on a region from the peripheral wafer edge of z (x<z) or less. An interlayer insulating film is formed on the whole wafer surface.

Abstract: In a wafer edge neighboring region 26, the circumference end part of a silicon oxide film 8 is set in an outer position than the circumference end part of a silicon oxide film 3 and thereby a structure in which polishing remains 21 generated in forming a copper interconnection comprising a copper film 6 and the like are covered with the silicon oxide film 8 is attained.

Abstract: A method for forming a multilayer interconnection structure on a wafer by using a damascene technique includes the steps of separating the area of the wafer into a peripheral area, an intermediate area and a central area as viewed from the outer periphery toward the center of the wafer The lower-level interconnections having a smaller width are formed in the intermediate and central areas, whereas the upper-level interconnections having a larger width are formed in the central area.

Abstract: An insulating layer is formed on a whole surface of a wafer. Recesses such as wiring grooves are formed in the insulating layer. A part of the insulating layer is removed on a region whose distance from the peripheral edge of the wafer is a value x or less. After a conductive film is formed on the whole wafer surface, a part is removed on a region whose distance from the peripheral wafer edge is a value y (y<x) or less. Chemical mechanical polishing removes a part of the conductive except in the recesses. Thereafter, wet etching removes part of the conductive film on a region from the peripheral wafer edge of z (x<z) or less. An interlayer insulating film is formed on the whole wafer surface.