Patents by Inventor Manabu Shibata

Manabu Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5476112
    Abstract: An apparatus for cleaning stainless steel or aluminum shutter members in a blanked and generally U-shaped form as they are fed continuously comprises a guide rail for guiding the shutter members so that they are transferred in a specified direction and a plurality of cleaning nozzles through which a cleaning solution is sprayed onto the shutter members. A plurality of vessels for supplying the cleaning solution to the Cleaning nozzles are provided along the guide rail and the cleaning solution overflowing a supply vessel downstream the guide rail is allowed to flow into sequentially upstream supply vessels via flow lines. The cleaning solution is recovered from the most upstream supply vessel and, after the cleaning debris is separated out, the cleaning solution is supplied into the most downstream supply vessel. The apparatus enables efficient cleaning of the shutter members.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: December 19, 1995
    Assignee: Kao Corporation
    Inventors: Tadashi Matsui, Mamoru Kinuta, Manabu Shibata
  • Patent number: 5377136
    Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: December 27, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Akira Uragami, Manabu Shibata, Yoshitatsu Kojima, Fumiaki Matsuzaki
  • Patent number: 5265045
    Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: November 23, 1993
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Akira Uragami, Manabu Shibata, Yoshitatsu Kojima, Fumiaki Matsuzaki
  • Patent number: 5168342
    Abstract: In a semiconductor integrated circuit device adopting a master slice system, a plurality of lattice points of an X-Y lattice-shaped channel region set by an automatic arrangement and routing system correspond to one input/output terminal of a prescribed basic cell (or logic circuit), thereby a plurality of signal wirings can be connected to the one input/output terminal.
    Type: Grant
    Filed: May 23, 1991
    Date of Patent: December 1, 1992
    Assignee: Hitachi, Ltd.
    Inventor: Manabu Shibata
  • Patent number: 5053644
    Abstract: A semiconductor integrated circuit is so designed that it is possible to form any one of the three different kinds of circuit configuration, that is, an inverter circuit, a Schmitt circuit and a common-mode circuit, as desired, by employing circuit elements prepared in advance and by changing wiring. Also disclosed is a semiconductor integrated circuit having these circuit configurations. The output stage of any one of the three kinds of circuit is constituted by a bipolar transistor, and the other portions are constituted by MOS field-effect transistors.
    Type: Grant
    Filed: May 16, 1986
    Date of Patent: October 1, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Shibata, Akira Uragami, Shinji Kadono, Yukio Suzuki
  • Patent number: 5017993
    Abstract: A semiconductor integrated circuit device, in which a system including a plurality of modules (functional blocks) such as a microprocessor unit and a memory unit is integrated on the main surface of a single semiconductor substrate, and each module of the system is connected through its corresponding interface circuits to the external terminals. The external terminals and the interface circuits are provided on the main surface of said semiconductor substrate, and are connected through an internal bus line commonly used between said modules. Also, and commonly use or internal bus line is connected directly to said external terminals to permit connection to a common external bus line.
    Type: Grant
    Filed: February 20, 1990
    Date of Patent: May 21, 1991
    Assignee: Hitachi, Ltd.
    Inventor: Manabu Shibata
  • Patent number: 4838939
    Abstract: Compositions particularly adapted to the damping sheet are provided. They contain a binder component and a filler component consisting of inorganic fillers and an organic filler.The organic filler occupies from 1 to 25 parts by weight of the total amount of the filler and it is an organic fibrous filler having the fiber length of from about 50 to about 300.mu., the mean length being about 100.mu.. Quick lime occupies from 0.05 to 10 parts by weight of the total amount of the filler as one of the inorganic fillers. The compositions possess distinguished properties when used as the damping sheet for vehicles.
    Type: Grant
    Filed: December 17, 1987
    Date of Patent: June 13, 1989
    Assignees: Nihon Tokushu Toryo Co., Ltd., Hirotani Co., Ltd.
    Inventors: Shigeru Kanda, Manabu Shibata, Masayoshi Ono, Michikazu Okano
  • Patent number: 4683384
    Abstract: An integrated circuit having the circuit construction wherein a plurality of each of input and output circuits are formed in such a manner as to form pairs and to correspond to a plurality of external connection pads, respectively, and are used selectively to replace the function of an internal circuit. A signal transmission path of an input circuit formed so as to correspond to an external connection pad to which an external input signal is applied at an input portion and at least part of a signal transmission path of an output circuit formed so as to correspond to the external connection pad are connected in series between the external connection pad and an input terminal of the internal circuit in order to use the signal transmission function of the output circuit as the function of the internal circuit.
    Type: Grant
    Filed: August 11, 1986
    Date of Patent: July 28, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Shibata, Akira Uragami