Patents by Inventor Manabu Takakuwa

Manabu Takakuwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152218
    Abstract: According to the embodiments, a template in which a main pattern is placed on a pattern-formed surface of a template substrate, the main pattern being formed by a concave and convex pattern, the template substrate being transparent to an electromagnetic wave with a predetermined wavelength is provided. The template includes a first mark in which line-shaped first concave patterns and first convex patterns are alternately placed in a width direction on the pattern-formed surface. The first convex pattern includes a first light-blocking portion and a first translucent portion. The first light-blocking portion is a region including a first side surface in the width direction and being covered with a metal film. The first translucent portion is a region including a second side surface in the width direction and being not covered with the metal film.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Manabu Takakuwa
  • Publication number: 20210294205
    Abstract: An exposure method includes acquiring first height information through detection of a height of an upper surface of a substrate subjected to exposure; acquiring first position information through detection of a relative position between the substrate and a first mask having a first pattern to be transferred on the substrate; converting the first height information to second position information; acquiring second height information through detection of a height of the upper surface of the substrate; acquiring third position information through detection of a relative position between the substrate and a second mask having a second pattern to be transferred on the substrate; converting the second height information to fourth position information; calculating differential position information, based on difference between the second position information and the fourth position information; and aligning the second mask and the substrate, based on the third position information and the differential position informa
    Type: Application
    Filed: September 2, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Hayato TERAI, Manabu TAKAKUWA
  • Publication number: 20210296152
    Abstract: According to one embodiment, there is provided a semiconductor manufacturing apparatus including a rotatable substrate stage, a first measuring mechanism and a second measuring mechanism. On the rotatable substrate stage, a laminated substrate used for manufacturing a semiconductor device is placed. The laminated substrate is formed by a first substrate and a second substrate to be laminated to each other. The first measuring mechanism measures an edge of the first substrate and an edge of the second substrate from a first direction. The second measuring mechanism measures the edge of the first substrate and the edge of the second substrate from a second direction. The second direction is a direction different from the first direction in an angle to a normal of the first substrate.
    Type: Application
    Filed: December 10, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Satoshi NAGAI, Manabu TAKAKUWA, Satoshi USUI
  • Publication number: 20210078317
    Abstract: According to one embodiment, there is provided a substrate bonding apparatus including a first suction stage, a second suction stage, and a pressing member. The first suction stage sucks a first substrate. The second suction stage is arranged so as to face the first substrate. The second suction stage sucks the second substrate. The pressing member is capable of deforming the first substrate sucked on the first suction stage so as to be convex toward the second suction stage side. The pressing member has a marking structure on a distal end side.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Hayato TERAI, Manabu TAKAKUWA
  • Publication number: 20210066068
    Abstract: A semiconductor wafer according to an embodiment includes a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region. The outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region.
    Type: Application
    Filed: February 18, 2020
    Publication date: March 4, 2021
    Applicant: Kioxia Corporation
    Inventors: Takashi KOIKE, Manabu Takakuwa
  • Patent number: 10921722
    Abstract: According to one embodiment, there is provided an exposure apparatus which projects a pattern of an original onto a substrate by a projection optical system so as to expose the substrate. The exposure apparatus includes a substrate stage, an alignment detecting system, and a controller. The substrate stage holds the substrate on which shot areas each including multiple chip areas are placed. The alignment detecting system detects multiple first alignment marks placed in a peripheral region in a first chip area in the shot area. The controller obtains the first amount of positional deviation for the first chip area according to results of detecting the multiple first alignment marks and controls exposure conditions for the first chip area in the shot area according to the first amount of positional deviation.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Manabu Takakuwa
  • Patent number: 10627726
    Abstract: According to one embodiment, a patterning support system includes an absolute position measuring device that measures absolute positions with respect to absolute coordinates, of a first pattern formed in a shot area of a substrate and a second pattern to be transferred to the substrate while being overlayed on the first pattern, a substrate profile measuring device that measures a global positional deviation amount of the substrate, a misalignment inspecting device that measures a misalignment amount of the second pattern with respect to the first pattern, a correction executing device that corrects the position of the second pattern with respect to the first pattern, and a control device that calibrates the absolute positions measured by the absolute position measuring device, using at least one of the global positional deviation amount and the misalignment amount, and converts the calibrated absolute positions into a position correction parameter to be used when the position of the second pattern is correct
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: April 21, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Manabu Takakuwa
  • Publication number: 20200019073
    Abstract: According to one embodiment, a patterning support system includes an absolute position measuring device that measures absolute positions with respect to absolute coordinates, of a first pattern formed in a shot area of a substrate and a second pattern to be transferred to the substrate while being overlayed on the first pattern, a substrate profile measuring device that measures a global positional deviation amount of the substrate, a misalignment inspecting device that measures a misalignment amount of the second pattern with respect to the first pattern, a correction executing device that corrects the position of the second pattern with respect to the first pattern, and a control device that calibrates the absolute positions measured by the absolute position measuring device, using at least one of the global positional deviation amount and the misalignment amount, and converts the calibrated absolute positions into a position correction parameter to be used when the position of the second pattern is correct
    Type: Application
    Filed: March 4, 2019
    Publication date: January 16, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Manabu TAKAKUWA
  • Publication number: 20190271922
    Abstract: According to one embodiment, there is provided an exposure apparatus which projects a pattern of an original onto a substrate by a projection optical system so as to expose the substrate. The exposure apparatus includes a substrate stage, an alignment detecting system, and a controller. The substrate stage holds the substrate on which shot areas each including multiple chip areas are placed. The alignment detecting system detects multiple first alignment marks placed in a peripheral region in a first chip area in the shot area. The controller obtains the first amount of positional deviation for the first chip area according to results of detecting the multiple first alignment marks and controls exposure conditions for the first chip area in the shot area according to the first amount of positional deviation.
    Type: Application
    Filed: September 6, 2018
    Publication date: September 5, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Manabu TAKAKUWA
  • Patent number: 10295409
    Abstract: According to one embodiment, a value of a film thickness of a processing object disposed above a substrate is obtained. Then, a wavelength that provides a highest degree of intensity of signal light reflected when the signal light is incident onto the processing object having the value of the film thickness, based on wavelength selection reference information is selected. Then, a first instruction performing an alignment process to the substrate by use of signal light having a wavelength thus selected is generated. The wavelength selection reference information is information that includes a correlation between values of the film thickness of the processing object and degrees of intensity of the signal light, with respect to a plurality of wavelengths.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Miki Toshima, Satoshi Usui, Manabu Takakuwa, Nobuhiro Komine, Takaki Hashimoto
  • Patent number: 10283392
    Abstract: According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress applied to the device area, and correcting an exposure condition in a lithography process of the device area based on the position gap of the predetermined point.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 7, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Manabu Takakuwa
  • Patent number: 10276459
    Abstract: According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. The method includes dividing the plurality of shot regions into a plurality of groups corresponding to a layer attribute based on the acquired layer information. The method includes deciding a measurement condition of a measuring apparatus for each of the plurality of groups. The plurality of layers are sequentially stacked on the substrate to manufacture a semiconductor device.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kenji Konomi, Manabu Takakuwa
  • Patent number: 10241397
    Abstract: According to one embodiment, an imprint apparatus including multiple types of imprint units and a conveyor to convey a substrate is provided. Each of the imprint units includes a suction mechanism configured to hold the substrate with multiple suction portions on a substrate holder, and a template having an imprint surface on which a concavo-convex pattern is formed on one face of a template substrate and having a recessed region in the other face, the recessed region corresponding to the imprint surface. The imprint units have different depths of the recessed regions in the templates and different arrangements of the suction portions in the suction mechanisms depending on the types.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: March 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Manabu Takakuwa, Yoshihisa Kawamura, Ikuo Yoneda
  • Patent number: 10093044
    Abstract: In an imprinting apparatus according to one embodiment, rear surfaces of first and second templates are suctioned. A correction information calculating device calculates a second response coefficient of the second template out of first response coefficients based on a flatness relational expression and flatness of the second template. The first response coefficients are actual amounts of positional slippage of the first template from a first input adjustment value. The flatness relational expression indicates a relationship between flatness of the first template and the first response coefficients. A shape and a size of the second template are adjusted using the second response coefficient.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshio Mizuta, Manabu Takakuwa, Masato Suzuki
  • Publication number: 20180269116
    Abstract: According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. The method includes dividing the plurality of shot regions into a plurality of groups corresponding to a layer attribute based on the acquired layer information. The method includes deciding a measurement condition of a measuring apparatus for each of the plurality of groups. The plurality of layers are sequentially stacked on the substrate to manufacture a semiconductor device.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 20, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kenji KONOMI, Manabu TAKAKUWA
  • Publication number: 20180233389
    Abstract: According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress applied to the device area, and correcting an exposure condition in a lithography process of the device area based on the position gap of the predetermined point.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Manabu TAKAKUWA
  • Patent number: 9966284
    Abstract: According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress applied to the device area, and correcting an exposure condition in a lithography process of the device area based on the position gap of the predetermined point.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Manabu Takakuwa
  • Patent number: 9966316
    Abstract: According to one embodiment, deposition supporting system, depositing apparatus and manufacturing method of a semiconductor device includes a depositing apparatus that deposits stacked bodies on wafers allocated to stations and a host computer. The host computer evaluates feature amounts convertible to misalignments at predetermined points on the stacked bodies of the respective wafers, and specifies the stations to which the wafers are to be allocated based on the feature amounts of the stacked bodies in the respective stations. The depositing apparatus allocates the wafers to the stations based on the specification from the host computer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Manabu Takakuwa
  • Patent number: 9952505
    Abstract: According to one embodiment, an imprint device includes a holding unit, a mounting unit, a moving unit, a curing unit, a pressing portion, and a detecting portion. The holding unit holds template having a pattern portion pressed onto a transfer portion provided on a substrate. The mounting unit mounts the substrate. The moving unit is provided on at least either the holding unit or the mounting unit. The moving unit moves the holding unit and the mounting unit in directions approaching each other or directions away from each other. The curing unit cures the transfer portion onto which the pattern portion of the template is pressed. The pressing portion pushes the template pressed onto the transfer portion in a direction intersecting a pressing direction of the template. The detecting portion detects a position of the template pushed by the pressing portion.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yosuke Okamoto, Nobuhiro Komine, Kazuhiro Segawa, Manabu Takakuwa, Kentaro Kasa
  • Patent number: 9941177
    Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kentaro Kasa, Kazuya Fukuhara, Kazutaka Ishigo, Manabu Takakuwa, Yoshinori Hagio, Kazuhiro Segawa, Yuki Murasaka, Tetsuya Kugimiya, Yuu Yamayose, Yosuke Okamoto