Patents by Inventor Manabu Yanagihara
Manabu Yanagihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7375407Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a substrate; and a high-resistance region formed in the first semiconductor layer and the second semiconductor layer and having higher resistance than the first semiconductor layer and the second semiconductor layer. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer in a portion surrounded with the high-resistance region.Type: GrantFiled: November 14, 2005Date of Patent: May 20, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
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Patent number: 7368793Abstract: The semiconductor device of the present invention includes a device formation region formed on a substrate and including at least one semiconductor region, and a first electrode and a second electrode formed spaced apart from each other on the device formation region. A semi-insulating film is formed to cover the surface of a portion of the semiconductor region, which portion is located between the first and second electrodes and in which portion a depletion layer extends when a reverse bias is applied between the first and second electrodes.Type: GrantFiled: March 17, 2005Date of Patent: May 6, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Manabu Yanagihara, Daisuke Ueda
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Publication number: 20080079023Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.Type: ApplicationFiled: August 7, 2007Publication date: April 3, 2008Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 7332754Abstract: In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.Type: GrantFiled: December 28, 2004Date of Patent: February 19, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Uno, Manabu Yanagihara, Hidetoshi Ishida, Tsuyoshi Tanaka
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Publication number: 20070284653Abstract: A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group Ill-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.Type: ApplicationFiled: April 20, 2007Publication date: December 13, 2007Inventors: Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 7291872Abstract: In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.Type: GrantFiled: August 1, 2005Date of Patent: November 6, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Hikita, Hiroaki Ueno, Yutaka Hirose, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Publication number: 20070235768Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.Type: ApplicationFiled: April 2, 2007Publication date: October 11, 2007Inventors: Kazushi Nakazawa, Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Publication number: 20070210332Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.Type: ApplicationFiled: March 2, 2007Publication date: September 13, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroaki UENO, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
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Publication number: 20070176215Abstract: A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.Type: ApplicationFiled: November 16, 2006Publication date: August 2, 2007Inventors: Manabu Yanagihara, Masahiro Hikita, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Publication number: 20070170463Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.Type: ApplicationFiled: December 29, 2006Publication date: July 26, 2007Inventors: Hiroaki Ueno, Manabu Yanagihara, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
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Publication number: 20070126115Abstract: A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.Type: ApplicationFiled: November 7, 2006Publication date: June 7, 2007Inventors: Manabu Yanagihara, Hiroaki Ueno, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Publication number: 20070126026Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.Type: ApplicationFiled: November 6, 2006Publication date: June 7, 2007Inventors: Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 7217960Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.Type: GrantFiled: January 5, 2006Date of Patent: May 15, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Ueno, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
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Publication number: 20070096151Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.Type: ApplicationFiled: November 21, 2006Publication date: May 3, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Manabu Yanagihara, Naohiro Tsurumi, Tsuyoshi Tanaka, Daisuke Ueda
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Patent number: 7148557Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.Type: GrantFiled: August 29, 2003Date of Patent: December 12, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Manabu Yanagihara, Naohiro Tsurumi, Tsuyoshi Tanaka, Daisuke Ueda
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Publication number: 20060273347Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.Type: ApplicationFiled: May 15, 2006Publication date: December 7, 2006Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 7132703Abstract: A field-effect transistor includes: a carrier supply layer supplying carriers; a Schottky contact layer forming a Schottky barrier; and an intermediate layer formed between the carrier supply layer and the Schottky contact layer. Here, the intermediate layer has an electron affinity which is higher than an electron affinity of the carrier supply layer but lower than an electron affinity of the Schottky contact layer.Type: GrantFiled: December 20, 2004Date of Patent: November 7, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Hikita, Manabu Yanagihara
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Publication number: 20060197175Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.Type: ApplicationFiled: March 1, 2006Publication date: September 7, 2006Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tsuyoshi Tanaka
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Publication number: 20060157729Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.Type: ApplicationFiled: January 5, 2006Publication date: July 20, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroaki Ueno, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
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Publication number: 20060108605Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a substrate; and a high-resistance region formed in the first semiconductor layer and the second semiconductor layer and having higher resistance than the first semiconductor layer and the second semiconductor layer. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer in a portion surrounded with the high-resistance region.Type: ApplicationFiled: November 14, 2005Publication date: May 25, 2006Inventors: Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda