Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.

Abstract: In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.

Abstract: The present invention, which aims at providing a semiconductor switch capable of reducing harmonic distortion, is made up of: an input terminal 101; an output terminal 102; a through FET 106 that is connected serially to the signal path between the input terminal 101 and the output terminal 102; a shunt FET 107 that is connected in between the output terminal 102 and the ground; and a distortion reducing circuit 120 that is connected in parallel with the through FET 106. In this semiconductor switch, the distortion reducing circuit 120 includes: a first diode 109 and a second diode 110 that are placed in parallel with each other; a first constant voltage source 111 and a second constant voltage source 112 that are placed in parallel with each other; and a FET 108.

Abstract: The semiconductor device of the present invention includes a device formation region formed on a substrate and including at least one semiconductor region, and a first electrode and a second electrode formed spaced apart from each other on the device formation region. A semi-insulating film is formed to cover the surface of a portion of the semiconductor region, which portion is located between the first and second electrodes and in which portion a depletion layer extends when a reverse bias is applied between the first and second electrodes.

Abstract: In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.

Abstract: A field-effect transistor includes: a carrier supply layer supplying carriers; a Schottky contact layer forming a Schottky barrier; and an intermediate layer formed between the carrier supply layer and the Schottky contact layer. Here, the intermediate layer has an electron affinity which is higher than an electron affinity of the carrier supply layer but lower than an electron affinity of the Schottky contact layer.

Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

Abstract: A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.

Abstract: A bipolar transistor includes: a first semiconductor layer having an intrinsic base region and an extrinsic base region; and a second semiconductor layer having a portion located on the intrinsic base region to be an emitter region or a collector region. A capacitive film is provided on the extrinsic base region using the same semiconductor material as that for the second semiconductor layer. A base electrode is formed on the first semiconductor layer to cover the capacitive film and the extrinsic base region.

Abstract: The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on the base layer in the shape of a ring along the outer circumference of the base layer, the semiconductor layer includes a ring-shaped emitter region functioning as an emitter, and the outer edge of the emitter region and the outer edge of the base layer are disposed in substantially the same plane position.

Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

Abstract: The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.

Abstract: An inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit transistors, each including a base, an emitter and a collector. In the planar layout of the device, a position of a first one of the transistors is shifted from a position of a second one of the transistors in a direction in which the banks extend. The first and second transistors belong to first and second ones of the banks, respectively, which are adjacent to each other. The second transistor is closer to the first transistor than any other transistor in the second bank.

Abstract: The invention provides a bipolar transistor attaining large MSG and a method of fabricating the same. The bipolar transistor of this invention includes a collector layer; abase layer deposited on the collector layer; and a semiconductor layer deposited on the base layer in the shape of a ring along the outer circumference of the base layer, the semiconductor layer includes a ring-shaped emitter region functioning as an emitter, and the outer edge of the emitter region and the outer edge of the base layer are disposed in substantially the same plane position.

Abstract: A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.

Abstract: A lower resist film, which is made of PMMA for EB exposure and has a thickness of about 200 nm, is applied onto a substrate, and then an upper resist film to be exposed to i-rays is applied on the lower resist film. Thereafter, a mixed layer, in which the upper and lower resist films are mixed, is formed in the interface between the upper and lower resist films. Next, the upper resist film, except for the head-forming region thereof, is exposed to i-rays and developed, thereby forming an upper-layer opening. And then the mixed layer and a leg-forming region of the lower resist film are exposed to EB and developed, thereby forming a lower-layer opening having an upper part like a taper progressively expanding upward.

Abstract: An ohmic electrode for a p-type III-V compound semiconductor is disclosed. The ohmic electrode formed on a p-type III-V compound semiconductor layer includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.

Abstract: A dummy emitter is formed in the portion corresponding to an emitter region, on a multiplayer structural material comprising layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of emitter region is formed, while the dummy emitter is inverted into an emitter electrode, thereby forming an emitter electrode metal layer to cover the whole upper surface of the emitter. Using thus formed emitter electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacently to the emitter.

Abstract: A bipolar transistor with improved high-frequency performance is invented. The improvement is attained by eliminating a parasitic base-collector capacitance. The invented transistor is constructed upon a semi-insulating substrate, and wherein a region which underlies an extrinsic base region is semi-insulative such that the extrinsic base region does not substantially overlap the collector contact region and the collector region when viewed in the direction perpendicular to the substrate. Here, it's worthwhile to point out that a portion under the extrinsic base region is made completely semi-insulative down to the substrate. As a result, the transistor has substantially no parasitic base-collector capacitance.

Abstract: A dummy emitter (a dummy collector, in an inverted type) is formed in the portion corresponding to an emitter (a collector, in the inverted type) region, on a multiplayer structural material including layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of the emitter (the collector, in the inverted type) region is formed, while the dummy emitter (the dummy collector, in the inverted type) is inverted into an emitter (a collector, in the inverted type) electrode, thereby forming an emitter (a collector, in the inverted type) electrode metal layer covering the whole upper surface of the emitter (the collector, in the inverted type). Using the thus formed emitter (the collector, in the inverted type) electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacent to the emitter (the collector, in the inverted type).