Patents by Inventor Manfred Eller
Manfred Eller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9209088Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.Type: GrantFiled: August 1, 2007Date of Patent: December 8, 2015Assignee: Infineon Technologies AGInventors: Manfred Eller, Jin-Ping Han
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Patent number: 9209181Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.Type: GrantFiled: June 14, 2013Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
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Publication number: 20150340501Abstract: Methods for producing independent-gate FinFETs with improved channel mobility and the resulting devices are disclosed. Embodiments may include forming an independent-gate fin field-effect transistor (FinFET) above a substrate; and forming stress within the fin between two independent gates of the independent-gate FinFET.Type: ApplicationFiled: May 22, 2014Publication date: November 26, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Xusheng WU, Johannes Marinus VAN MEER, Manfred ELLER, Vara Govindeswara Reddy VAKADA
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Publication number: 20150243563Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Bongki LEE, Jin Ping LIU, Manoj JOSHI, Manfred ELLER, Rohit PAL, Richard J. CARTER, Srikanth Balaji SAMAVEDAM
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Publication number: 20150243658Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Manoj JOSHI, Manfred ELLER, Richard J. CARTER, Srikanth Balaji SAMAVEDAM
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Publication number: 20150243652Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Manoj JOSHI, Manfred ELLER, Rohit PAL, Richard J. CARTER, Srikanth Balaji SAMAVEDAM, Bongki LEE, Jin Ping LIU
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Patent number: 9087720Abstract: A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.Type: GrantFiled: August 4, 2014Date of Patent: July 21, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Xusheng Wu, Changyong Xiao, Manfred Eller, Wanxun He, Jie Chen
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Patent number: 9082698Abstract: One illustrative method disclosed includes, among other things, forming a fin in a substrate, forming a well implant region in at least the substrate, forming a punch-stop implant region in the fin, performing at least one neutral implantation process with at least one neutral implant material to form a neutral boron-diffusion-blocking implant region in the fin, wherein an upper surface of the neutral boron-diffusion-blocking implant region is positioned closer to an upper surface of the fin than either the punch-stop implant region or the well implant region and, after forming the well implant region, the punch-stop implant region and the neutral boron-diffusion-blocking implant region, forming a gate structure above the fin.Type: GrantFiled: March 7, 2014Date of Patent: July 14, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Manoj Joshi, Johannes Marinus van Meer, Manfred Eller
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Patent number: 9070759Abstract: A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.Type: GrantFiled: September 25, 2006Date of Patent: June 30, 2015Assignee: Infineon Technologies AGInventors: Jin-Ping Han, Haoren Zhuang, Jiang Yan, Jingyu Lian, Manfred Eller
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Publication number: 20150140756Abstract: Circuit fabrication methods are provided which include, for example: providing one or more gate structures disposed over a substrate structure, the substrate structure including a first region and a second region; forming a plurality of U-shaped cavities extending into the substrate structure in the first region and the second region thereof, where at least one first cavity of the plurality of U-shaped cavities is disposed adjacent in one gate structure in the first region; and expanding the at least one first cavity further into the substrate structure to at least partially undercut the one gate structure, without expanding at least one second cavity of the plurality of U-shaped cavities, where forming the plurality of U-shaped cavities facilitates fabricating the circuit structure. In one embodiment, the circuit structure includes first and second transistors, having different device architectures, the first transistor having a higher mobility characteristic than the second transistor.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Hong YU, Seong Yeol MUN, Bingwu LIU, Lun ZHAO, Richard J. CARTER, Manfred ELLER
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Publication number: 20140367787Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Vara G. Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna, Srikanth Balaji Samavedam, Sri Charan Vemula, Manfred Eller
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Publication number: 20140353757Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.Type: ApplicationFiled: July 3, 2014Publication date: December 4, 2014Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
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Patent number: 8846476Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.Type: GrantFiled: February 14, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yanxiang Liu, Manfred Eller, Johannes van Meer
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Patent number: 8809958Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.Type: GrantFiled: November 15, 2011Date of Patent: August 19, 2014Assignee: Infineon Technologies AGInventors: Henning Haffner, Manfred Eller, Richard Lindsay
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Publication number: 20140227845Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.Type: ApplicationFiled: February 14, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Yanxiang Liu, Manfred Eller, Johannes van Meer
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Patent number: 8431972Abstract: An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration.Type: GrantFiled: December 13, 2006Date of Patent: April 30, 2013Assignee: Infineon Technologies AGInventors: David Alvarez, Richard Lindsay, Manfred Eller, Cornelius Christian Russ
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Patent number: 8242550Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece having a first orientation and at least one second orientation. The semiconductor device is implanted with a dopant species using a first implantation process in the first orientation of the workpiece. The semiconductor device is implanted with the dopant species using a second implantation process in the at least one second orientation of the workpiece, wherein the second implantation process is different than the first implantation process.Type: GrantFiled: July 2, 2010Date of Patent: August 14, 2012Assignee: Infineon Technologies AGInventors: Thomas Schiml, Manfred Eller
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Publication number: 20120074499Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.Type: ApplicationFiled: November 15, 2011Publication date: March 29, 2012Applicant: Infineon Technologies AGInventors: Henning Haffner, Manfred Eller, Richard Lindsay
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Patent number: 8078998Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.Type: GrantFiled: July 20, 2010Date of Patent: December 13, 2011Assignee: Infineon Technologies AGInventors: Henning Haffner, Manfred Eller, Richard Lindsay
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Patent number: 8012821Abstract: Generating an embedded resistor in a semiconductor device includes forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed above the STI region; etching the silicon layer to yield a polyconductor above the STI region; oxidizing the polyconductor; depositing an oxide material or a metal gate material on the oxidized surface; depositing a silicon layer on the oxide material or metal gate material; depositing additional silicon on a portion of the silicon layer above the STI region; patterning a transistor gate with a photo-resist mask on another portion of the silicon layer away from the STI region; and etching the silicon layer to yield a transistor structure away from the STI region and a resistor structure above the STI region.Type: GrantFiled: February 3, 2009Date of Patent: September 6, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Choongryul Ryou, Seunghwan Lee, Jun Yuan, Victor Chan, Manfred Eller, Nam Sung Kim, Narasimhulu Kanike, Srikanth Balaji Samavedam