Abstract: An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.

Abstract: The invention provides a method for testing a circuit unit (101) to be tested, in which a test time is reduced, at least one word line (102a-102N) of the circuit unit (101) to be tested being activated by application of at least one test signal (103) to the word line (102a-102N), the at least one word line (102a-102N) being deactivated by removal of the test signal (103) from the word line (102a-102N), the word lines among all the word lines (102a-102N) which have not run through an activation-deactivation cycle being read out in order to determine an influence of the activation and deactivation, and the test result being output.