Abstract: In a method for fabricating an LSI in which primitive devices such as transistors are formed on a semiconductor substrate and a plurality of interconnect layers are formed thereover to provide sub-circuits of successively larger scale and increasing complexity including sub-circuits which are formed by a connection of the primitive devices and sub-circuits of a larger scale which are formed by a connection of the sub-circuits, under a condition that an intermediate interconnect layer is formed, an exhaustive test, a functional test, a stuck-at fault test, a quiescent power supply current test or the like takes place with respect to the primitive devices or the sub-circuits which are wired together by the intermediate interconnect layer, and subsequently, a wiring connection test takes place after the formation of each subsequent interconnect layer. A fault coverage is improved while a testing cost and a fabricating cost are reduced.

Abstract: There is provided a method and an apparatus for detecting a delay fault in a phase-locked loop circuit. A frequency impulse is applied to the PLL circuit under test as a reference clock, and a waveform of a signal outputted from the PLL circuit under test is transformed to an analytic signal to estimate its instantaneous phase. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay fault is detected by comparing a time duration during which the PLL circuit stays in a state of oscillating a certain frequency with the time duration during which a fault-free PLL circuit stays in a state of oscillating a certain frequency.

Abstract: There is provided a method of and an apparatus for detecting delay faults in phase-locked loop circuits. A frequency impulse is applied to a phase-locked loop circuit under test as the reference clock, and a waveform of a signal outputted from the phase-locked loop circuit under test is transformed to an analytic signal to estimate an instantaneous phase of the analytic signal. A linear phase is estimated from the estimated instantaneous phase, and the estimated linear phase is removed from the estimated instantaneous phase to obtain a fluctuation term of the instantaneous phase. A delay time is measured from this fluctuation term of the instantaneous phase, and further, a delay fault is detected by comparing a time duration during which the phase-locked loop circuit remains in a state of oscillating a certain frequency with a time duration during which a fault-free phase-locked loop circuit remains in a state of oscillating that certain frequency.

Abstract: This invention is an apparatus and method for monitoring and motivating user compliance for orthodontic headgear (24) of the type using a linear spring force module (22). The spring force module (22) includes first (38) and second opposite attachment members that are interconnected to provide spring tension when moved linearly apart. A position sensor (16)(18)(19) detects liner movement between the attachment members. A microprocessor (12) receives signals from the position sensor to determine wear duration, force magnitude, and whether such movement is sufficiently variable to be biological in origin or is attempted mimicry. Multiple determinations made by the processor are recorded over time to provide an evaluation of headgear wear compliance and to provide ongoing motivation for user compliance.