Abstract: A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.

Abstract: The invention provides for improved performance of out of sequence load operations. The system has an improved compiler, with an optimizer, an improved CPU with four new instructions in its instruction set, and an address compare unit (ACU). During compilation, the improved compiler identifies load operations that can be move out of sequence ahead of associated store operations and moves those load operations out of sequence and flags them as such. The associated store operations are also flagged. During processor execution of a compiled and optimized program, the address of operands fetched by the out of sequence load operations are saved to the new associative memory. On request, the ACU compares the addresses saved to the addresses generated by the associated store operations.

Abstract: A sense amplifier apparatus for use in a memory array having a plurality of memory cells is provided. The sense amplifier apparatus includes a differential sense amplifier and a dynamic sense amplifier. The differential sense amplifier has a first set of switches for driving the voltages of the sense amplifier apparatus and are coupled to a complementary pair of outputs. Also provided are a second set of switches, which are coupled to a complementary pair of input lines so as to amplify the input signal on either of the pair of input lines to a first signal level at a first rate of amplification. The dynamic sense amplifier shares the first set of switches with the differential sense amplifier and further includes a third set of switches that are coupled to a complementary pair of input lines and the output lines and also a sense enable line. This allows the first signal level to be amplified to a second signal level at a second rate of amplification faster than the first rate of amplification.

Abstract: Benes networks are very effective in providing inter-processor communication in SIMD parallel machines, provided the communication patterns are compile-time determinable. These networks are ill suited when communication patterns are dynamically varying because of the long set up time requirements. The present invention is a method for handling dynamically varying communication patterns efficiently by operating the Benes network in a time division multiplexed manner, wherein during a given transmission period, the middle stage switches of the Benes network are configured as a portion of the middle stage switches of a Clos network configured to route all signals in a single period.

Abstract: A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

Abstract: A computer system processes mixed control, indexing and data manipulation instructions in groups of N instructions at a time. A group of instructions is applied to a set of N Dispatch units which execute the control and indexing instructions directly. The Dispatch Units convert data manipulation instructions into a more primitive data flow operations. The data flow operations are applied to a set of M Execution Units which process the operations concurrently by observing data dependency constraints. The data used by the control and indexing instructions is stored in a group of identical memory structures which are accessible by each of the Dispatch Units. Data for the data manipulation instructions is stored in a data structure which is divided among the Execution Units.

Abstract: A method of switching data packets through a multistage interconnection network (MIN), to prevent hot spot traffic from degrading uniform traffic performance. Each of the address bits in each packet determine the output link at each particular stage of the network to which the packet must be routed. A packet is accepted at an input buffer of the stage only if an acceptance test is met. This acceptance test depends not only on the availability of a buffer at the input buffer at a stage of the network, but also on how the address bits of the packet are related to address bits of other packets in the buffer, and on the stage of the network. If the acceptance test is not met, the packet is retained in the previous stage of the MIN, and is moved to the rear of a queue of packets in the buffer at that stage, or given a lower priority in the queue.

Abstract: A method and apparatus used to detect errors in a signal transmitted over a single wire. All transient errors are detected when the effect of the transient lasts for at least one cycle and not more than five cycles. Transient errors of longer duration will be detected if the level of the original signal at the start of the transient is different from that at the end of the transient. Stuck faults will be deleted if one onset of the stuck fault causes the level of the signal to change. Redundancy is incorporated by introducing redundant transitions in the signal on the same wire. This requires the successive transitions in the original signal to be at least three cycles apart. If a transition is viewed as a binary one and the absence of a transition as a binary zero then each binary one is replaced with the sequence "one-one-one" (overwriting subsequent zeros), and keeping each zero as the single bit "zero". Upon decoding, each group of three transitions is converted to a single transition.

Abstract: A method of switching synchronous and asynchronous data packets through a multi-stage interconnection network (MIN), so as to insure that packets with the highest assignable priority level will never be blocked at any stage of the network. More specifically, this invention relates to a method of switching voice and data packets over the MIN wherein each of the address bits in each packet determine the connection to be established at each particular stage in the network and wherein each packet has therein a priority level. In each time slot of a frame, the priority level of the packets stored in a particular originating adapter are compared and the packet with the highest priority level in each adapter is forwarded through the MIN and routed through the MIN as described above. Also, at each subswitch at each stage of the MIN, if two or more packets request the same subswitch output, only the packet with the higher priority is forwarded to the subswitch output.

Abstract: The objects of the invention are the provision of an improved food product of the type having a smooth, continuous aqueous phase with discrete pulp-simulating particles dispersed therein and to an improved process for preparing products of this type which could withstand the processing conditions of heat and shear.According to the present invention, products of this type are improved by employing as the pulp-simulating particles from about 1 to 10%, based upon the weight of the products, of bread crumbs consisting essentially of wheat flour, yeast and salt, the bread crumbs having a porous, striated and elongated shape and structure and a particle size wherein they are retained on a USS 60 mesh screen after passing a USS 16 mesh screen. These bread crumbs readily absorb moisture from the aqueous phase to provide soft yet coherent pulp-like particles which enhance the appeal of food products, such as barbeque sauces and simulated fruit sauces.