Abstract: A method for allowing flexible creation and alteration of business processes within a commerce system includes using state machines to describe the actions that can be taken by particular roles at particular points in a process. The state machines are used by a commerce system to enforce validity of user actions, to track the execution of actions within an instance of the business process, to provide the user interface with a list of actions available to a user working on an instance of the business process, to provide coordination between state machines, and to allow different organizations to have varied business processes.

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses.

Abstract: A keeper circuit (14) is included in a memory arrangement comprising a column of memory cells (20) connected by a bit line pair (16,18). The keeper circuit (14) comprises two keeper transistors. One keeper transistor (86) is connected to control current from a supply voltage source to one bit line (16) and the other keeper transistor (88) is connected to control current from the supply voltage source to the other bit line (18) of the bit line pair. Current through each keeper transistor (86, 88) is controlled by the charge state of the opposite bit line. A low charge state on one bit line causes the keeper transistor associated with the opposite bit line to conduct and maintain the charge level of the opposite bit line.

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses.

Abstract: A write driver apparatus (10) is adapted for producing a first data output signal and a second data output signal used in driving data onto a bit line pair (16, 18) associated with an electronic computer memory. The first and second data output signals represent desired data and are produced in response to a data signal, refill signal, and a data propagation clock signal. The data propagation signal is derived from system clock signals. A precharge circuit (12) associated with the write driver (10) operates in response to a precharge clock signal to precharge the bit lines (16, 18) prior to each read or write operation. The precharge clock signal is related to the data propagation signal to ensure that the bit lines (16, 18) are fully precharged prior to a read operation. A keeper circuit (14) associated with the bit lines (16, 18) also helps maintain a desired charge state on the bit lines during a read operation from memory cells (20) connected to the bit lines.

Abstract: A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for enabling the sense amplifier when there is a hit in the array as a result of a read request and disables the sense amplifier when there is a miss in the array as a result of the read request. The cache memory device may receives an address associated with the read request, and compares the address to addresses associated with entries in the array, wherein a hit results when the received address matches at least one of the addresses associated with the entries in the array, and wherein a miss results when the received address does not match at least one of the addresses associated with the entries in the array. The address associated with the read request and the addresses associated with entries in the array are effective addresses.

Abstract: A dynamic sense amplifier (10) cooperates with an embedded latch arrangement for converting signals read from a memory cell array to digital signals. The dynamic sense amplifier (10) is connected to a complementary pair of data output lines, each associated with a data output node, and to a complementary pair of data lines from a column decoder associated with the memory cell array. The dynamic sense amplifier (10) is also connected to a sense enable line for receiving a sense enable signal, while the latch incorporated in the dynamic sense amplifier (10) is connected to a latch enable line. The dynamic sense amplifier (10) operates to quickly develop an intermediate charge state at the data output nodes in response to a read charge state on the data lines and a sense enable signal applied at the sense enable line. After developing the intermediate charge state, the latch enable signal is applied to the latch enable line to take the intermediate charge state to a final charge state at the data output nodes.

Abstract: A write driver apparatus (10) is adapted for producing a first data output signal and a second data output signal used in driving data onto a bit line pair (16, 18) associated with an electronic computer memory. The first and second data output signals represent desired data and are produced in response to a data signal, refill signal, and a data propagation clock signal. The data propagation signal is derived from system clock signals. A precharge circuit (12) associated with the write driver (10) operates in response to a precharge clock signal to precharge the bit lines (16, 18) prior to each read or write operation. The precharge clock signal is related to the data propagation signal to ensure that the bit lines (16, 18) are fully precharged prior to a read operation. A keeper circuit (14) associated with the bit lines (16, 18) also helps maintain a desired charge state on the bit lines during a read operation from memory cells (20) connected to the bit lines.

Abstract: A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

Abstract: A method and apparatus for delivering multimedia video data from a server (host processor) to a plurality of clients connected to a communications network. More specifically, with this invention, preprocessed video and multimedia data packets are striped across disks in units of fixed playback time, even if such units result in variable length stripes. To deliver multiple video or continuous media streams, the disks in the array are accessed simultaneously so that at any given instance, different disks are accessing the video or multimedia data for different streams. Access to the disks for reading the continuous media files is scheduled periodically, with the period equal to the back time of the stripes. Because each disk read command retrieves data for a fixed play back time, if the first read command for a continuous media stream request can be scheduled to complete on a disk within a playback time, all subsequent read commands are also guaranteed to not interfere with read commands of other streams.

Abstract: The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths.

Abstract: An address gating circuit for a memory array having redundant word lines. The address gating circuit includes a plurality of address lines comprising paired true and complement address lines for receiving address bits. The true and complement values of the address lines are ORed together then the results are ANDed together to generate an output. The output is used to inhibit selection of one of the address lines until a latest address bit is received.

Abstract: Benes networks are used in SIMD single instruction multiple data parallel processing systems to provide interprocessor communication. The invention describes an algorithm which will allow these networks to be used in presence of several faults, without reducing their interconnection capability.

Abstract: A method and apparatus for delivering multimedia video data from a server (host processor) to a plurality of clients connected to a communications network. More specifically, with this invention, preprocessed video and multimedia data packets are stored in switches of the network. When a client desires to receive the video and multimedia data, sends a request to the host processor which in turn sends a control message to the switches storing the requested data. These switches in turn send the requested data to the requesting client. If the data is not stored in the switches, the data must then be forwarded directly from the server to the requesting client.

Abstract: The invention is a method and system which provides consultants, business process analysts, and application developers with a unified tool with which to conduct business process analysis, design, documentation and to generate business process definitions and workflow-enabled applications. The invention may be implemented using a software system which has two functional sets. One is a set of graphical tools that can be used by a developer or business analyst to map out business processes. The second is a set of tools that can be used to document and specify in detail the attributes of each workflow definition, including roles, cycle time, conditions, of satisfaction, cost and value, associated text, forms, application data as well as detail the attributes of links between workflows required to complete a business process map, and to generate a business process definition and a workflow-enabled application.

Abstract: A method for removing particulate contaminants from a semiconductor wafer is disclosed. A wafer 10 is held in a wafer holder 12 at cleaning station 14. Cleaning station 14 has a rinse fluid supply system 18 which supplies, e.g. deionized water, to the wafer surface during particle removal. A cleaning pad 20 is mounted on a platen 22, substantially in the plane of wafer 10. Platen 22 is coupled to a drive mechanism 24, which may for example be an electric motor, and drive mechanism 24 is coupled to station 14 by an engagement mechanism 26 which provides vertical displacement to engage pad 20 and wafer 10 for particle removal, and also provides a controlled pad contact pressure during particle removal. In operation, rinse fluid from 18 is supplied to slowly rotating wafer 10, while pad 20 is rotated, preferably at 200 to 600 rpm, and contacted with wafer 10.

Abstract: A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g.

Abstract: A single instruction multiple data stream ("SIMD") processor includes multiple processing elements ("PEs"). Each PE includes a memory, a first multiplexer, an instruction register, a local instruction buffer for storing an instruction and a unit for modifying the instruction, in its entirety, to create a modified instruction. The modified instruction is stored in the local instruction buffer until it is executed. This structure modifies the instruction broadcast from the central controller of an SIMD computer in its entirety and creates modified instructions which can be unique to each PE.

Abstract: A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.

Abstract: Multiselection of word lines is eliminated in a memory array which includes a word line generation circuit which inhibits line selection until a latest address bit is received.