Abstract: The present invention pertains to forming respective silicides on multiple transistors in a single process. High performance is facilitated with simple and highly integrated process flows. As such, transistors, and an integrated circuit containing the transistors, can be fabricated efficiently and at a low cost. The different silicides can be formed with different materials and/or to different thicknesses. As such, the silicides can have different electrical characteristics, such as resistivity and conductivity. These different attributes instill the transistors with different work functions when formed as gate contacts thereon. This provides an integrated circuit containing the transistors with diverse operating capabilities allowing for the execution of operations requiring more flexibility and/or functionality.

Abstract: The present invention pertains to forming respective suicides on multiple transistors in a single process. High performance is facilitated with simple and highly integrated process flows. As such, transistors, and an integrated circuit containing the transistors, can be fabricated efficiently and at a low cost. The different suicides can be formed with different materials and/or to different thicknesses. As such, the silicides can have different electrical characteristics, such as resistivity and conductivity. These different attributes instill the transistors with different work functions when formed as gate contacts thereon. This provides an integrated circuit containing the transistors with diverse operating capabilities allowing for the execution of operations requiring more flexibility and/or functionality.

Abstract: A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: According to one embodiment of the invention, a method for manufacturing a transistor is provided. The method includes masking a polysilicon layer of a semiconductor device to have a dimension greater than a critical dimension of a gate to be formed. The polysilicon layer overlies a substrate layer. The method also includes incompletely etching the polysilicon layer. The method also includes forming a source region and a drain region in the substrate layer through the incompletely etched polysilicon layer by doping the substrate layer and applying heat at a first temperature. The method also includes forming a source extension and a drain extension in the substrate layer after forming the source region and the drain region by doping the substrate layer and applying heat at a second temperature.

Abstract: A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.

Abstract: A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an active area on the substrate. A polysilicon gate (14) is formed, on top of the gate oxide, by etching. Etch damage (16) on the substrate surface is repaired by anneal in an inert gas environment—e.g., He, Ne, N2, Ar gas, or combinations thereof.

Abstract: A semiconductor device and method for reducing dopant loss includes forming a gate electrode of an MOS transistor adjacent a semiconductor substrate. A relatively thin oxide screen layer is formed and disposed outwardly from the gate electrode. Nitrogen is then incorporated into the oxide screen layer. An upper dielectric layer is formed such that it is disposed outwardly from the nitrided oxide screen layer.

Abstract: Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage. This causes the effective channel length of the low Vt transistors to be shorter than that of the core transistors, which causes lower threshold voltage.

Abstract: A method of forming a semiconductor device includes doping at least one region of an at least partially formed semiconductor device. The method further includes depositing at least one spacer layer outwardly from the at least one region of the at least partially formed semiconductor device. The at least one deposited spacer layer is formed in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the at least partially formed semiconductor device.

Abstract: A process (10) for the production of a transistor device with reduced gate depletion is disclosed. The system includes providing a semiconductor substrate, forming a gate dielectric on an active area on the upper surface portion of the substrate and depositing a gate layer on top of the gate oxide. Next, the gate is implanted (12) with Boron and the N-doped regions of gate are patterned (14) and implanted (16).

Abstract: A system for fabricating an integrated circuit is disclosed that includes providing a semiconductor substrate (10), and forming a gate oxide layer (12) on an active area on the substrate. A polysilicon gate (14) is formed, on top of the gate oxide, by etching. Etch damage (16) on the substrate surface is repaired by anneal in an inert gas environment—e.g., He, Ne, N2, Ar gas, or combinations thereof.

Abstract: A method (40) of forming an integrated circuit (60) device comprising a substrate (64). The method comprises the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack comprising a gate having sidewalls. The method further comprises the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further comprises the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer comprises depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C.

Abstract: A method of fabricating a transistor comprises forming a gate structure outwardly of a semiconductor substrate, wherein the gate structure comprises a gate, a gate insulator and sidewalls and forming source region and a drain region in the substrate using the gate structure as a mask, wherein a channel is defined in the substrate between the source region and the drain region. A bottomwall/sidewall junction capacitance reduction region extending within and between the source region and the drain region is formed, wherein the bottomwall/sidewall junction capacitance reduction region extends at least partially through the bottomwall junction or the sidewall junction.

Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract: The present invention relates to a method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: Low threshold voltage transistors are fabricated by removing oxide spacers from the poly gate sidewalls of the transistors that are to be low threshold voltage. This causes the effective channel length of the low Vt transistors to be shorter than that of the core transistors, which causes lower threshold voltage.